k4d263238a-gc50 Samsung Semiconductor, Inc., k4d263238a-gc50 Datasheet - Page 4

• Manufacturer Part Number: k4d263238a-gc50
• Description: 1m X 32bit X 4 Banks Double Data Rate Synchronous Ram With Bi-directional Data Strobe And Dll
• Manufacturer: Samsung Semiconductor, Inc.

GENERAL DESCRIPTION
K4D26323RA-GC
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM
with Bi-directional Data Strobe and DLL
FEATURES
ORDERING INFORMATION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
• 2.8V + 5% power supply for device operation
• 2.8V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive
• Differential clock input
• No Wrtie-Interrupted by Read Function
The K4D26323RA is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by
32 bits, fabricated with SAMSUNG
extremely high performance up to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
going edge of the system clock
-. Read latency 3,4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
K4D26323RA-GC2A
K4D26323RA-GC33
K4D26323RA-GC36
Part NO.
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
Max Freq.
350MHz
300MHz
275MHz
* VDD / VDDQ=2.8V *
- 4 -
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 350MHz
• Maximum data rate up to 700Mbps/pin
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
(VDD/VDDQ=2.8V)
Interface
SSTL_2
128M DDR SDRAM
Rev. 2.0 (Jan. 2003)
144-Ball FBGA
Package