ic42s16100 ETC-unknow, ic42s16100 Datasheet - Page 16

• Manufacturer Part Number: ic42s16100
• Description: 512k X 16 Bit X 2 Banks 16-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16100
OPERATION COMMAND TABLE
16
Current State Command
Write Recovery DESL
With Auto-
Precharge
Refresh
Mode Register DESL
Set
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input
2. All input signals are latched on the rising edge of the CLK signal.
3. Both banks must be placed in the inactive (idle) state in advance.
4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.
5. The row address is generated automatically internally at this time. The I/O pin and the address pin data is ignored.
6. During a self-refresh operation, all pin data (states) other than CKE is ignored.
7. The selected bank must be placed in the inactive (idle) state in advance.
8. The selected bank must be placed in the active state in advance.
9. This command is valid only when the burst length set to full page.
10. This is possible depending on the state of the bank selected by the A11 pin.
11. Time to switch internal busses is required.
12. The IC42S16100 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state.
13. The IC42S16100 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state.
14. Possible if t
15. Illegal if t
16. The conditions for burst interruption must be observed. Also note that the IC42S16100 will enter the precharged state
17. Command input becomes possible after the period t
18. A8,A9 = don't care.
Input pins other than CKE are ignored at this time.
Input pins other than CKE are ignored at this time.
immediately after the burst operation completes if auto-precharge is selected.
precharged state immediately after the burst operation completes if auto-precharge is selected.
RAS
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
RRD
is not satisfied.
is satisfied.
No Operation, Idle State After t
Illegal
Illegal
Operation
No Operation, Idle State After t
No Operation, Idle State After t
Illegal
Illegal
Illegal
Illegal
No Operation, Idle State After t
No Operation, Idle State After t
No Operation, Idle State After t
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
No Operation, Idle State After t
No Operation, Idle State After t
No Operation, Idle State After t
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
(10)
(10)
(10)
(10)
(1,2)
RCD
has elapsed. Also note that the IC42S16100 will enter the
DAL
DAL
DAL
RP
RP
RP
MCD
MCD
MCD
Has Elapsed
Has Elapsed
Has Elapsed
Has Elapsed
Has Elapsed
Has Elapsed
Has Elapsed
Has Elapsed
Has Elapsed
CS
CS
CS
CS
CS RAS
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
RAS
RAS
RAS CAS
Integrated Circuit Solution Inc.
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
X
L
L
L
L
X
L
L
L
L
CAS
CAS
CAS
CAS WE
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
WE
WE
WE
WE A11 A10 A9-A0
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
DR024-0D 06/25/2004
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
X
OP CODE
OP CODE
OP CODE
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
X
X
X
X
V
V
V
V
X
V
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)