ic42s16100 ETC-unknow, ic42s16100 Datasheet - Page 27

• Manufacturer Part Number: ic42s16100
• Description: 512k X 16 Bit X 2 Banks 16-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16100
Interval Between Read Command
A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding
to the new write command can be input in place of the data
for the previous write command.
CAS latency = 2, burst length = 4
CAS latency = 2, burst length = 4
COMMAND
COMMAND
CLK
CLK
I/O
I/O
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
WRITE A0 WRITE B0
D
READ A0
IN
A0
D
READ B0
IN
t
t
CCD
CCD
B0
D
OUT
D
IN
A0
B1
D
OUT
D
IN
B0
B2
The interval between two read command (t
least one clock cycle.
The selected bank must be set to the active state before
executing this command.
The interval between two write commands (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
D
OUT
IN
B3
B1
D
OUT
B2
D
OUT
B3
CCD
CCD
) must be at
) must be
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