ic42s16100 ETC-unknow, ic42s16100 Datasheet - Page 33

• Manufacturer Part Number: ic42s16100
• Description: 512k X 16 Bit X 2 Banks 16-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16100
Write Cycle (Full Page) Interruption Using
The IC42S16100 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IC42S16100 repeats the operation starting at the 256th
cycle with data input returning to location (a) and continuing
with a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command
Burst Data Interruption Using the
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the CAS latency, two clock cycles (t
LDQM pins goes HIGH, the corresponding outputs go to
the HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
CAS latency = 2, 3, burst length = full page
CAS latency = 2, burst length = 4
the Burst Stop Command
U/LDQM Pins (Read Cycle)
COMMAND
COMMAND
I/O8-I/O15
I/O0-I/O 7
UDQM
LDQM
CLK
CLK
I/O
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
WRITE A0
D
READ A0
IN
QMD
A0
DATA MASK (UPPER BYTE)
) after one of the U/
D
IN
A1
DATA MASK (LOWER BYTE)
t
QMD=2
D
D
D
IN
OUT
OUT
A
A0
A0
D
D
IN
OUT
A1
must be executed within the ACT to PRE command period
(t
period (t
the execution of the burst stop command has elapsed, the
write cycle terminates. This period (t
cycles, regardless of the CAS latency.
LOW, output is resumed at a time t
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
I/O8-I/O15) and the LDQM pin controlling lower byte
output (pins I/O0 to I/O7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
RAS
HI-Z
A1
max.) following the burst stop command. After the
D
IN
D
WBD
OUT
A2
HI-Z
) required for burst data input to stop following
BURST STOP
A2
BST
D
INVALID DATA
t
OUT
WBD=0
A3
PRECHARGE (BANK 0)
PRE 0
HI-Z
t
RP
QMD
WBD
later. This output
) is zero clock
Don’t Care
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