m69ar024b STMicroelectronics, m69ar024b Datasheet
m69ar024b
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m69ar024b Summary of contents
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... Mbit (1M x16) 1.8V Supply, Asynchronous PSRAM FEATURES SUMMARY SUPPLY VOLTAGE: 1.7 to 2.25V ACCESS TIME: 70ns, 80ns LOW STANDBY CURRENT: 110µA DEEP POWER DOWN CURRENT: 10µA COMPATIBLE WITH STANDARD LPSRAM TRI-STATE COMMON I/O March 2005 M69AR024B Figure 1. Package FBGA TFBGA48 (ZB) 6x8mm 1/28 ...
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... M69AR024B TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A19 Data Inputs/Outputs (DQ8-DQ15 Data Inputs/Outputs (DQ0-DQ7 Chip Enable (E1 Chip Enable (E2 Output Enable (G Write Enable (W) ...
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... Figure 22.Standby Mode Entry AC Waveforms, After Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 23.TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm Pitch, Package Outline, Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 10. TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm Pitch, Package Mechanical Data . . 25 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 M69AR024B 3/28 ...
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... M69AR024B SUMMARY DESCRIPTION The M69AR024B Mbit (16,777,216 bit) CMOS memory, organized as 1,048,576 words by 16 bits, and is supplied by a single 1.7V to 2.25V supply voltage range. M69AR024B is a member of STMicroelectronics 1T/1C (one transistor per cell) memory family. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area ...
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... DQ8 DQ9 A5 A6 DQ10 V SS A17 A7 DQ11 A16 DQ12 DQ14 A14 A15 DQ13 DQ15 A12 A13 A19 A18 A8 A9 A10 M69AR024B DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 W DQ7 A11 NC AI05861b 5/28 ...
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... M69AR024B SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access dur- ing Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The ...
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... Figure 4. Block Diagram INTERNAL GENERATOR ADDRESS CONTROL CONTROLLER V SS ARBITRATION LOGIC CLOCK REFRESH CONTROLLER DYNAMIC MEMORY ARRAY INPUT/OUTPUT BUFFER COLUMN DECODER LOGIC ADDRESS POWER M69AR024B DQ0-DQ7 DQ8-DQ15 AI07261b 7/28 ...
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... W, E1, E2, LB and UB as summarized in the Operating Modes table (see 2., Operating Modes). Power Up Sequence Because the internal control logic of the M69AR024B needs to be initialized, the following power-on procedure must be followed before the memory is used: – Apply power and wait for V – ...
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... Valid Valid Valid (1) (1) (1) (1) ( M69AR024B I DQ0-DQ7 DQ8-DQ15 CC I Hi-Z Hi-Z SB (4) Hi-Z Hi Hi-Z Hi-Z CC Output I Hi-Z CC Valid Output I Hi-Z CC Valid Output Output I CC Valid Valid I Invalid Invalid CC I Invalid ...
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... M69AR024B MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicat- Table 3. Absolute Maximum Ratings ...
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... Min 1.7 – 0. Figure 6. AC Measurement Load Circuit DEVICE UNDER TEST 0.7V CC 0.3V CC AI04831 C L includes JIG capacitance M69AR024B M69AR024B Max 2. 0. Unit V °C ...
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... M69AR024B Table 5. Capacitance Symbol C Input Capacitance on all pins (except DQ) IN (2) Output Capacitance C OUT Note: 1. Sampled only, not 100% tested. 2. Outputs deselected. Table 6. DC Characteristics Symbol Parameter I CC1 V Active Current CC I CC2 I Input Leakage Current LI I Output Leakage Current LO I Deep Power Down Current ...
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... Applicable when at least two of address inputs among applicable are switched from previous state (min) must be satisfied. AVAX Parameter V = 1.7V to 2.25V 1.8V to 2.25V CC (min). AVAX termination M69AR024B M69AR024B 70 80 Min Max Min Max 80 80 1000 1000 70 70 –5 – ...
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... M69AR024B Figure 7. Address Controlled, Read Mode AC Waveforms A0-A19 tAVEL E1 G LB, UB DQ0-DQ15 Note High High. Figure 8. Address and Output Enable Controlled, Read Mode AC Waveforms tAXAV A0-A19 E1 G UB, LB DQ0-DQ15 Note High High. 14/28 ADDRESS VALID tELEH tELQV tGLQV tBLQV tBLQX tGLQX tELQX ...
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... Figure 9. LB/UB Controlled, Read Mode AC Waveforms tAXAV A0-A19 tAVQV E1 Low tBLQV LB UB tBLQX DQ0-DQ7 DQ8-DQ15 Note Low High Low High. tAVAX ADDRESS VALID tBLQV tBHQZ tBLQV tBHQX tBLQX VALID DATA OUT tBLQX VALID DATA OUTPUT M69AR024B tAXAV tBHQZ tBHQX VALID DATA OUT tBHQZ tBHQX ai09383 15/28 ...
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... Write Cycle Time t WC ELAX (3) t Chip Enable Low to Chip Enable High t CW ELEH (7) t Output Enable High to Address Valid t OES GHAV 16/28 Parameter V = 1.7V to 2.25V 1.8V to 2.25V CC M69AR024B 70, 80 Unit Min Max 80 1000 1000 ...
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... DQ0-DQ15 Note High. Parameter , the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought tELAX ADDRESS VALID tELEH tWLWH tBLBH tDVEH tDVWH tDVBH M69AR024B M69AR024B 70, 80 Min Max –5 15 1000 1000 , and write recovery time ( ...
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... M69AR024B Figure 11. Write Enable Controlled, Write AC Waveforms A0-A19 E1 Low tAVWL W LB DQ0-DQ15 Note High. Figure 12. Write Enable and UB/LB Controlled, Write AC Waveforms 1 A0-A19 E1 Low tAVWL DQ0-DQ7 DQ8-DQ15 Note High. 18/28 tAVAX ADDRESS VALID tAXAV tWHAX tWLWH tAVWL tGHAV tDVWH tGHDZ tWHDZ ...
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... VALID DATA INPUT tAVAX ADDRESS VALID tAXAV tAXAV tBLBH tBHAX tAVBL tWHBL tDVBH tBHDZ VALID DATA INPUT M69AR024B tAVAX ADDRESS VALID tAXAV tWHAX tBHWL tWHBL tBLWH tDVWH tWHDZ VALID DATA INPUT AI09387b tAVAX ADDRESS VALID tAXAV tBHWL tWHBL ...
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... M69AR024B Figure 15. Write Enable and UB/LB Controlled, Write AC Waveforms 4 A0-A19 E1 Low W tAVBL LB DQ0-DQ7 tAVBL UB DQ8-DQ15 Note High. 20/28 tAVAX ADDRESS VALID tAXAV tAXAV tBHAX tBLBH tBLBH2 tDVBH tBHDZ VALID DATA INPUT tBLBH tAVBL tDVBH tBHDZ VALID DATA INPUT tAVAX ADDRESS VALID tAXAV tBLBH ...
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... WRITE DATA INPUT tELAX WRITE ADDRESS tAVEL tWHAX tWLWH tEHEL tGHEL tGLQV tGLQX tDVWH tWHDZ WRITE DATA INPUT M69AR024B tELAX(read) READ ADDRESS tAVEL tEHAX(read) (read) tELQV tELQX tEHQX ai09390 tELAX(read) READ ADDRESS tAVEL tEHAX(read) (read) tELQV tGHQX READ DATA ...
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... M69AR024B Figure 18. Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms tAXAV A0-A19 E1 Low tAVWL W UB tGHQZ tGHQX DATA DQ0-DQ15 OUT Note: E1 can be tied Low for a W and G controlled operation. When E1 is tied Low, the output is exclusively controlled by G. ...
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... The Input Transition Time ( testing is 5ns as shown below. If actual t is longer than 5ns, it may violate AC specification of some timing parameters. Figure 20. Power Down Mode AC Waveforms E1 E2 tCLEX DQ0-DQ15 Parameter (min) is not satisfied. EHWL tEXCH Power-Down Entry Power-Down Mode M69AR024B M69AR024B 70, 80 Min Max 10 70 300 300 tEHCH ...
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... M69AR024B Figure 21. Power-Up Mode AC Waveforms E1 E2 VCC Figure 22. Standby Mode Entry AC Waveforms, After Read E1 tEHGL G W Read Active Note High. 24/28 tEHEV VCCmin tEHWL Standby Write Active AI09395 Standby AI09396 ...
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... M69AR024B ddd A2 BGA-Z26 inches Typ Min 0.0102 0.0138 0.2362 0.2323 0.1476 – 0.3150 0.3110 0.2067 – 0.0295 – 0.0443 – ...
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... T = Tape & Reel Packing The notation used for the device number is as shown in list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office. 26/28 M69AR024B Table 11., Ordering Information T Scheme. For a ...
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... Table 8., Write Mode AC BHWL WHBL 13 and 14, Write Enable and UB/LB Controlled, Write AC Waveforms. Minor modification in first paragraph of Summary Description. t updated in Table 8., Write Mode AC ELEH M69AR024B , BLQZ ELQZ GLQZ (min) changed (min) and t (min) revised. EHEV CHEL and Table 8., Write Mode paragraph clarified and title of Table 8 ...
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... M69AR024B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...