m69aw048b STMicroelectronics, m69aw048b Datasheet
m69aw048b
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m69aw048b Summary of contents
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... WORD PAGE ACCESS CAPABILITY: 18ns WIDE OPERATING TEMPERATURE – –30 to +85°C A POWER-DOWN MODES – Deep Power-Down – 4 Mbit Partial Array Refresh – 8 Mbit Partial Array Refresh – 16 Mbit Partial Array Refresh November 2004 32 Mbit (2M x16) 3V Asynchronous PSRAM Figure 1. Package M69AW048B FBGA TFBGA48 (ZB) 6x8 mm 1/29 ...
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... M69AW048B TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A20 Data Inputs/Outputs (DQ8-DQ15 Data Inputs/Outputs (DQ0-DQ7 Chip Enable (E1 Chip Enable (E2 Output Enable (G Write Enable (W) ...
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... Figure 25.Standby Mode Entry AC Waveforms, After Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 26.TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View . . . . 26 Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 M69AW048B 3/29 ...
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... M69AW048B SUMMARY DESCRIPTION The M69AW048B Mbit (33,554,432 bit) CMOS memory, organized as 2,097,152 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range. M69AW048B is a member of STMicroelectronics PSRAM memory family. These devices are manu- factured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area ...
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... DQ14 G DQ15 A18 DQ10 A5 A6 A17 A7 DQ11 NC A16 DQ12 DQ13 A14 A15 A19 A12 A13 A8 A9 A10 M69AW048B DQ0 DQ1 DQ2 DQ3 V CC DQ4 V SS DQ5 DQ6 W DQ7 A11 A20 AI07242 5/29 ...
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... M69AW048B SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access dur- ing Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The ...
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... Figure 4. Block Diagram INTERNAL CLOCK GENERATOR ADDRESS CONTROL LOGIC POWER CONTROLLER V SS ARBITRATION LOGIC REFRESH CONTROLLER DYNAMIC MEMORY ARRAY INPUT/OUTPUT BUFFER COLUMN DECODER ADDRESS M69AW048B DQ0-DQ7 DQ8-DQ15 AI07221b 7/29 ...
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... W, E1, E2, LB and UB as summarized in the Operating Modes table (see 2., Operating Modes). Power-Up Sequence Because the internal control logic of the M69AW048B needs to be initialized, the following Power-Up procedure must be followed before the memory is used: – Apply power and wait for V – ...
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... V Hi Data Output ( Data Input Data Retention No 4 Mbit 8 Mbit 16 Mbit M69AW048B DQ8-DQ15 Power Hi-Z Standby ( Power-Down (I I Hi-Z CCPD, CCP4 CCP8, CCP16 Hi-Z Output Disable Hi-Z Active ( Active (I ) Hi-Z CC Hi-Z Output Disable Active (I ...
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... M69AW048B Table 4. Power-Down Program Sequence Cycle # Operation 1st Read 2nd Write 3rd Write 4th Write 5th Write 6th Read Note: 1. PDC Power-Down Configuration. Table 5. Power-Down Configuration Data Power-Down Modes DQ15–DQ9 Deep Power-Down 0 (default) 4Mb PAR 0 8Mb PAR 0 16Mb PAR 0 Table 6. Power-Down Configuration Addresses ...
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... CC V Input or Output Voltage IO these or any other conditions above those indicat the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter M69AW048B Min Max Unit – –30 85 °C –55 125 ° ...
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... The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 8. Figure 5. AC Measurement I/O Waveform I/O Timing Reference Voltage Output Timing Reference Voltage 12/29 Conditions summarized in AC Measurement check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. M69AW048B Min 2.7 – 0. and IL 5 ...
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... OUT 3.3V 0. –0.2V –0. 2.7V –0.5mA 1mA OL + 0.2V 1.0V for a period 5ns 1.0V for a period 5ns. SS M69AW048B Test Min Max Unit Condition OUT Min Max Unit / ...
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... In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page Read Cycle must be closed within 4µs. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied. 14/29 Parameter *0 M69AW048B Unit Min Max 70 1000 ns 25 ...
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... ADDRESS VALID tELQV tGLQV tBLQV tBLQX tGLQX VALID DATA OUTPUT tAVAX tAVAX ADDRESS VALID ADDRESS VALID tAVQV tAXAV tAVQV tGLQV tAXQX DATA OUT M69AW048B VALID tAVEL tEHAX tEHEL tEHQZ tGHQZ tBHQZ tEHQX AI08986 tAXAV tGHAX tGHQX tGHQZ DATA OUT AI08987 15/29 ...
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... M69AW048B Figure 9. UB/LB Controlled, Read Mode AC Waveforms tAXAV A0-A20 tAVQV E1 Low tBLQV LB UB tBLQX DQ0-DQ7 DQ8-DQ15 Note Low High Low High. Figure 10. Page Address and Chip Enable Controlled, Read Mode AC Waveforms A20-A3 tAVAX A2-A0 ADDRESS VALID tAVEL tELAX tAVQV tAXAV2 E tELQV G LB, UB tELQX ...
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... Note High. tAVAX tAVAX ADDRESS VALID tAXAV tAXAV2 tAVAX2 tAVAX ADDRESS ADDRESS VALID VALID tAVQV2 tAVQV tAXQX tAXQX DATA DATA OUT OUT (Page Access) (Normal Access) M69AW048B tAXAV tAVAX2 ADDRESS VALID tAVQV2 tAXQX tAXQX DATA DATA OUT OUT (Page Access) AI08992 17/29 ...
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... Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met. 18/29 Parameter Min ELEH WLBH BLBH M69AW048B Unit Max 70 1000 ...
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... VALID DATA INPUT tAVAX ADDRESS VALID ADDRESS VALID tWHAX tWLWH tAVWL tWLWH tDVWH tWHDX tDVWH VALID DATA INPUT M69AW048B ADDRESS VALID tEHAX tAVEL tWHAX tAVWL tBHAX tAVBL tEHDZ tWHDZ tBHDZ ai08993 tAVAX tWHAX tWHDZ VALID DATA INPUT ...
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... M69AW048B Figure 14. Write Enable and UB/LB Controlled, Write AC Waveforms 1 A0-A20 tAXAV E1 Low tAVWL DQ0-DQ7 DQ8-DQ15 Note High. Figure 15. Write Enable and UB/LB Controlled, Write AC Waveforms 2 tAXAV A0-A20 E1 Low tAVBL DQ0-DQ7 DQ8-DQ15 Note High. 20/29 tAVAX ADDRESS VALID ADDRESS VALID tWLBH tAVWL tWLBH ...
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... VALID DATA INPUT tBHAX tBLBH tAVBL tDVBH tBHDZ tDVBH VALID DATA INPUT M69AW048B tAVAX tBLBH tBHAX tBVWH tBHDZ VALID DATA INPUT AI08997b tAVAX tBLBH tBHAX tBHDZ VALID DATA INPUT tBLBH2 tBLBH tBHAX tBHDZ ...
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... M69AW048B Figure 18. Chip Enable Controlled, Read Followed by Write Mode AC Waveforms A0-A20 tEHAX (read) E1 tEHEL W UB, LB tGHEL G tEHQZ tEHQX READ DATA DQ0-DQ15 OUTPUT Note: Write address is valid from either last falling edge. Figure 19. E1 Controlled, Read and Write Mode AC Waveforms ...
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... WRITE ADDRESS READ ADDRESS tAXAV tAVQV tWLWH tWHAX tAVWL tAVGL tGLQX tDVWH tWHDZ DATA IN tAVAX tAVAX(read) WRITE ADDRESS READ ADDRESS tAXAV tAVQV tBLBH tBHAX tBLQV tAVGL tBLQX tDVBH tBHDZ DATA IN M69AW048B tGLQV tGHQZ tGHQX DATA OUT ai09401b tBHQZ tBHQX DATA OUT ai09402b 23/29 ...
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... Cycle 6, the Power Down Program is completed and the device returns to normal operation. EHEL 24/29 Parameter (min) is not satisfied. EHWL tAVAX MSB 2 MSB 2 MSB 2 tAXAV RDa RDa 00 Cycle 2 Cycle 3 Cycle 4 M69AW048B Unit Min Max 300 µs 1 µs 0 µ ...
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... DQ0-D15 Figure 24. Power-Up Mode AC Waveforms E1 E2 VDD Figure 25. Standby Mode Entry AC Waveforms, After Read Note High. tEXCH Power-Down Power-Down Mode Entry tEHEL VDDmin tEHGL tEHWL Read Active Standby Write Active M69AW048B tEHCH tCHEL Hi-Z Power-Down AI09403 Exit AI09404 Standby AI09405 25/29 ...
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... M69AW048B PACKAGE MECHANICAL Figure 26. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View FD FE BALL "A1" Note: Drawing is not to scale. Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data millimeters Symbol Typ 6.000 D1 3.750 ddd E 8 ...
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... Operative Temperature 8 = – °C The notation used for the device number is as shown in package, etc.) or for further information on any aspect of this device, please contact your nearest STMi- croelectronics Sales Office. M69AW048 Table 15.. For a list of available options (speed, M69AW048B 27/29 ...
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... M69AW048B REVISION HISTORY Table 16. Document Revision History Date Version 07-Oct-2002 -01 First Issue 10-Mar-2003 2.0 Document completely revised Data Key and Address Key renamed Power-Down Configuration data and Power-Down Configuration Address respectively. Sleep mode renamed Deep Power-Down mode. I removed and I CCS 9-Mar-2004 3.0 Partial mode renamed Partial Array Refresh. ...
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