mt18vdvf6472d Micron Semiconductor Products, mt18vdvf6472d Datasheet - Page 26
mt18vdvf6472d
Manufacturer Part Number
mt18vdvf6472d
Description
Ddr Sdram Vlp Registered Dimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT18VDVF6472D.pdf
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DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
44. I
45. Whenever the operating frequency is altered, not including jitter, the DLL is required
46. Leakage number reflects the worst case leakage possible through the module pin, not
47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
48. The -335 speed grade will operate with
I
remain stable. Although I
to be reset. This is followed by 200 clock cycles (before READ commands).
what each memory device contributes.
LOW.
at any slower frequency.
DD
DD
2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
2Q is similar to I
DD
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
2F except I
DD
26
2F, I
DD
2N, and I
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2Q specifies the address and control inputs to
t
RAS (MIN) = 40ns and
DD
2Q are similar, I
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
t
DD
RAS (MAX) = 120,000ns
2F is “worst case.”
Notes
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