mt18lsdt12872a Micron Semiconductor Products, mt18lsdt12872a Datasheet - Page 10
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mt18lsdt12872a
Manufacturer Part Number
mt18lsdt12872a
Description
Synchronous Dram Module
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT18LSDT12872A.pdf
(29 pages)
Figure 5:
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
Mode Register Definition Diagram
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
Program
12
A12
Reserved
11
A11
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
10
A10
WB
M9
0
1
9
A9
Op Mode
8
A8
7
A7
Programmed Burst Length
M8
10
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
A6
5
M7
A5
0
-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
A4
M3
BT
M6–M0
Defined
0
1
3
A3
-
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
A2
M1
M5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All Other States Reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
Mode Register Definition
A0
Full Page
Reserved
Reserved
Reserved
M3 = 0
Interleaved
Burst Type
Sequential
1
2
4
8
Mode Register (Mx)
Burst Length
Address Bus
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
©2002 Micron Technology, Inc. All rights reserved.
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8