mt5lsdt872ay-13e Micron Semiconductor Products, mt5lsdt872ay-13e Datasheet - Page 11

• Manufacturer Part Number: mt5lsdt872ay-13e
• Description: 32mb, 64mb, 128mb X72, Sr 168-pin Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Commands
Table, provides a general reference of available com-
mands. For a more detailed description of commands
Table 9:
CKE is HIGH for all commands shown except SELF REFRESH
NOTE:
32, 64, 128MB x 64 SDRAM DIMM
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ
burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output enable
Write Inhibit/Output High-Z
1. A0–A11 define the op-code written to the mode register, and for the 128MB module, A12 should be driven LOW.
2. A0–A11 (32MB and 64MB) or A0–A12 (128MB) provide device row address, and BA0, BA1 determine which device bank
3. A0–A7 (32MB) or A0–A8 (64MB and 128MB) provide device column address; A10 HIGH enables the auto precharge fea-
4. A10 LOW: BA0, BA1 determine the device bank being precharged. A10 HIGH: All device banks precharged and BA0, BA1
5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay).
Table 9, Commands and DQMB Operation Truth
is made active.
ture (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is
being read from or written to.
are “Don’t Care.”
Commands and DQMB Operation Truth Table
S#
H
L
L
L
L
L
L
L
L
–
–
RAS# CAS# WE# DQMB
11
X
H
H
H
H
L
L
L
L
–
–
and operations, refer to the 64Mb, 128Mb, or 256Mb
SDRAM component data sheet.
X
H
H
H
H
L
L
L
L
–
–
32MB, 64MB, 128MB (x72, SR)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
168-PIN SDRAM UDIMM
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
–
–
©2004 Micron Technology, Inc. All rights reserved.
High-Z
Active
Active
Valid
DQS
X
X
X
X
X
X
X
NOTES
5, 6
2
3
3
4
1
7
7