m393t5160qza Samsung Semiconductor, Inc., m393t5160qza Datasheet - Page 4

• Manufacturer Part Number: m393t5160qza
• Description: 240pin Registered Module Based On 1gb Q-die 72-bit Ecc
• Manufacturer: Samsung Semiconductor, Inc.

RDIMM
2.0 Features
1.0 DDR2 Registered DIMM Ordering Information
Note :
1. “Z” of Part number(11th digit) stands for Lead-Free and RoHS compliant products.
2. "J" of Part number(11th digit) stands for Lead-Free and RoHS compliant dual-die package products.
3. “3” of Part number(12th digit) stands for Non-parity Register products
4. "A" of Part number(12th digit) stands for Parity Register products.
3.0 Address Configuration
M393T2863QZA-CE7/F7/E6
M393T5663QZA-CE7/F7/E6
M393T5660QZA-CE7/F7/E6
M393T5160QZA-CE7/F7/E6
M393T1G60QJA-CE6/D5
M393T2863QZ3-CD5/CC
M393T5663QZ3-CD5/CC
M393T5660QZ3-CD5/CC
M393T5160QZ3-CD5/CC
Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
• Performance range
• JEDEC standard V
• V
• 200 MHz f
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• Average Refresh Period 7.8us at lower than a T
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 256Mx4/128Mx8, 63ball FBGA - DDP 512Mx4
• All of base components are Lead-Free, Halogen-Free, and RoHS compliant
CAS Latency
- Support High Temperature Self-Refresh rate enable feature
tRCD(min)
tRP(min)
tRC(min)
DDQ
Speed
256Mx4(1Gb) based Module
128Mx8(1Gb) based Module
Part Number
= 1.8V ± 0.1V
CK
Organization
for 400Mb/sec/pin, 267MHz f
DDR2-800 5-5-5
DD
= 1.8V ± 0.1V Power Supply
12.5
12.5
57.5
Density
5
1GB
2GB
2GB
4GB
8GB
1GB
2GB
2GB
4GB
Organization
128Mx72
256Mx72
256Mx72
512Mx72
128Mx72
256Mx72
256Mx72
512Mx72
1Gx72
CK
DDR2-800 6-6-6
Row Address
for 533Mb/sec/pin, 333MHz f
CASE
A0-A13
A0-A13
15
15
60
6
85°C, 3.9us at 85°C < T
DDP 512Mx4(K4T2G0404QQ)*36EA
128Mx8(K4T1G084QQ)*18EA
256Mx4(K4T1G044QQ)*18EA
256Mx4(K4T1G044QQ)*36EA
128Mx8(K4T1G084QQ)*18EA
256Mx4(K4T1G044QQ)*18EA
256Mx4(K4T1G044QQ)*36EA
128Mx8(K4T1G084QQ)*9EA
128Mx8(K4T1G084QQ)*9EA
Component Composition
DDR2-667 5-5-5
4 of 29
Column Address
15
15
60
5
A0-A9, A11
CK
CASE
A0-A9
for 667Mb/sec/pin, 400MHz f
< 95 °C
DDR2-533 4-4-4
15
15
60
4
Number of Rank
Bank Address
BA0-BA2
BA0-BA2
CK
1
2
1
2
4
1
2
1
2
for 800Mb/sec/pin
DDR2-400 3-3-3
DDR2 SDRAM
Rev. 1.1 July 2008
Parity Register
15
15
55
3
Auto Precharge
O
O
O
O
O
X
X
X
X
A10
A10
Units
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
tCK
ns
ns
ns
Height