hys64t256022hdl-5-a Infineon Technologies Corporation, hys64t256022hdl-5-a Datasheet - Page 22

• Manufacturer Part Number: hys64t256022hdl-5-a
• Description: 200-pin So-dimm Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

3.4
Table 14
Parameter
Operating Current 0
One bank Active - Precharge;
between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
t
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
SWITCHING, Data bus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are FLOATING.
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Active Power-Down Current
All banks open;
inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open; t
inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current
urst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING.
All Bank Interleave Read Current
All banks are being interleaved at minimum
and address bus inputs are STABLE during DESELECTS.
1)
Data Sheet
RCD
RAS
RAS
CK
CK
=
=
V
=
=
=
DDQ
t
t
CK.MIN
CK.MIN.
t
t
t
RAS.MAX
RAS.MAX.
RCD.MIN
= 1.8 V
., Refresh command every
, Refresh command every
Currents Specifications and Conditions
I
DD
, AL = 0, CL = CL
,
,
t
t
RP
RP
t
Measurement Conditions
CK
CK
0.1 V;
=
=
=
=
t
t
RP.MIN
RP.MAX
t
t
CK.MIN
CK.MIN
V
DD
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
= 1.8 V
, CKE is LOW; Other control and address inputs are STABLE, Data bus
, CKE is LOW; Other control and address inputs are STABLE, Data bus
t
MIN
CK
I
; CKE is HIGH, CS is HIGH between valid commands. Address and
=
DD6
t
0.1 V
CK.MIN
current values are guaranteed up to
t
I
t
RFC
RFC
OUT
t
CK
,
=
t
=
= 0 mA, BL = 4,
CK
Electrical CharacteristicsCurrents Specifications and Conditions
t
t
t
RC
RC
t
1)2)3)4)5)6)
=
REFI
RFC.MIN
=
t
without violating
=
CK.MIN
t
CK.MIN
interval, CKE is LOW and CS is HIGH between valid
t
I
RC.MIN
OUT
interval, CKE is HIGH, CS is HIGH between valid
; Other control and address inputs are STABLE,
; Other control and address inputs are
= 0 mA.
,
22
t
RAS
t
I
CK
out
=
=
t
= 0 mA.
t
RAS.MIN
RRD
t
Small Outline DDR2 SDRAM Modules
CK.MIN
using a burst length of 4. Control
, CKE is HIGH, CS is HIGH
,
t
RC
T
HYS64T256022HDL–[3.7/5]–A
=
CASE
MIN
t
MIN
RC.MIN
;
t
of 85 C max.
;
CK
t
CK
,
=
t
=
RAS
t
CK.MIN
t
CK.MIN
09092004-D30U-XRMR
=
t
RAS.MIN
;
;
Rev. 1.2, 2005-08
,
Symbol
I
I
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2N
DD2P
DD2Q
DD3N
DD3P(0)
DD3P(1)
DD4W
DD5B
DD5D
DD6
DD7