hys64t256022hdl-5-a Infineon Technologies Corporation, hys64t256022hdl-5-a Datasheet - Page 8

• Manufacturer Part Number: hys64t256022hdl-5-a
• Description: 200-pin So-dimm Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 5
Pin or Ball No.
107
106
85
102
101
100
99
98
97
94
92
93
91
105
90
89
116
Data Sheet
Pin Configuration of SO-DIMM (cont’d)
NC
AP
NC
Name
BA0
BA1
BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
Pin
Type
I
I
I
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Pin Configuration and Block DiagramsPin Configuration
8
Function
Bank Address Bus 2:0
Selects which DDR2 SDRAM internal bank of four or
eight is activated.
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Less than 1Gb DDR2 SDRAMS
Address Bus 12:0
During a Bank Activate command cycle, defines the
row address when sampled at the crosspoint of the
rising edge of CK and falling edge of CK. During a
Read or Write command cycle, defines the column
address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the
column address, AP is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If
AP is HIGH, autoprecharge is selected and BA0-BAn
defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge
command cycle, AP is used in conjunction with BA0-
BAn to control which bank(s) to precharge. If AP is
HIGH, all banks will be precharged regardless of the
state of BA0-BAn inputs. If AP is LOW, then BA0-BAn
are used to define which bank to precharge.
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Address Signal 13
Note: 1 Gbit based module
Not Connected
Note: Module based on 512 Mbit or smaller dies
Small Outline DDR2 SDRAM Modules
HYS64T256022HDL–[3.7/5]–A
09092004-D30U-XRMR
Rev. 1.2, 2005-08