mt9v034c12stmdes aptina, mt9v034c12stmdes Datasheet - Page 16

• Manufacturer Part Number: mt9v034c12stmdes
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Sequence
Bus Idle State
Table 6:
Data Bit Transfer
PDF: 09005aef8366edcb/Source: 09005aef8366ede5
MT9V034_DS - Rev. A 10/08 EN
Slave Address Modes
A typical READ or WRITE sequence begins by the master sending a start bit. After the
start bit, the master sends the slave device’s 8-bit address. The last bit of the address
determines if the request is a read or a write, where a “0” indicates a WRITE and a “1”
indicates a READ. The slave device acknowledges its address by sending an acknowledge
bit back to the master.
If the request was a WRITE, the master then transfers the 8-bit register address to which
a WRITE should take place. The slave sends an acknowledge bit to indicate that the
register address has been received. The master then transfers the data 8 bits at a time,
with the slave sending an acknowledge bit after each 8 bits. The MT9V034 uses 16-bit
data for its internal registers, thus requiring two 8-bit transfers to write to one register.
After 16 bits are transferred, the register address is automatically incremented, so that
the next 16 bits are written to the next register address. The master stops writing by
sending a start or stop bit.
A typical READ sequence is executed as follows. First the master sends the write mode
slave address and 8-bit register address, just as in the write request. The master then
sends a start bit and the read mode slave address. The master then clocks out the register
data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The
register address is automatically incremented after every 16 bits is transferred. The data
transfer is stopped when the master sends a no-acknowledge bit. The MT9V034 allows
for 8-bit data transfers through the two-wire serial interface by writing (or reading) the
most significant 8 bits to the register and then writing (or reading) the least significant 8
bits to Byte-Wise Address register (0x0F0).
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
One data bit is transferred during each clock pulse. The two-wire serial interface clock
pulse is provided by the master. The data must be stable during the HIGH period of the
serial clock—it can only change when the two-wire serial interface clock is LOW. Data is
transferred 8 bits at a time, followed by an acknowledge bit.
{S_CTRL_ADR1, S_CTRL_ADR0}
00
01
10
11
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16
MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor
Slave Address
0xB0
0xB1
0xB8
0xB9
0x90
0x91
0x98
0x99
Aptina Imaging reserves the right to change products or specifications without notice.
©2008 Aptina Imaging Corporation. All rights reserved.
Serial Bus Description
Write/Read Mode
Write
Write
Write
Write
Read
Read
Read
Read