mt9v034c12stmdes aptina, mt9v034c12stmdes Datasheet - Page 65
![no-image](/images/no-image-200.jpg)
mt9v034c12stmdes
Manufacturer Part Number
mt9v034c12stmdes
Description
1/3-inch Wide-vga Cmos Digital Image Sensor
Manufacturer
aptina
Datasheet
1.MT9V034C12STMDES.pdf
(82 pages)
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Row Binning
Column Binning
Figure 30:
PDF: 09005aef8366edcb/Source: 09005aef8366ede5
MT9V034_DS - Rev. A 10/08 EN
Readout of 8 Pixels in Normal and Row Bin Output Mode
By setting bit 0 or 1 of R0x0D or R0x0E, only half or one-fourth of the row set is read out,
as shown in Figure 30. The number of rows read out is half or one-fourth of the value set
in R0x03. The row binning result depends on the difference in pixel values: for pixel
signal differences less than 200 LSB's, the result is the average of the pixel values.
For pixel differences of 200 LSB's or more, the result is the value of the darker pixel value.
For column binning, either two or four columns are combined by averaging to create the
result. In setting bit 2 or 3 of R0x0D or R0x0E, the pixel data rate is slowed down by a
factor of either two or four, respectively. This is due to the overhead time in the digital
pixel data processing chain. As a result, the pixel clock speed is also reduced accordingly.
Row Bin 2 readout
Row Bin 4 readout
Normal readout
LINE_VALID
LINE_VALID
LINE_VALID
D
D
D
OUT
OUT
OUT
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Aptina Confidential and Proprietary
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65
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MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor
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Aptina Imaging reserves the right to change products or specifications without notice.
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©2008 Aptina Imaging Corporation. All rights reserved.
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Feature Description
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