mt9v034c12stmdes aptina, mt9v034c12stmdes Datasheet - Page 49
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mt9v034c12stmdes
Manufacturer Part Number
mt9v034c12stmdes
Description
1/3-inch Wide-vga Cmos Digital Image Sensor
Manufacturer
aptina
Datasheet
1.MT9V034C12STMDES.pdf
(82 pages)
- Current page: 49 of 82
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Figure 16:
Figure 17:
Slave Mode
PDF: 09005aef8366edcb/Source: 09005aef8366ede5
MT9V034_DS - Rev. A 10/08 EN
FRAME_VALID
Snapshot Mode Interface Signals
Snapshot Mode Frame Synchronization Waveforms
LINE_VALID
EXPOSURE
LED_OUT
D
OUT
(9:0)
xxx
In slave mode, the exposure and readout are controlled using the EXPOSURE,
STFRM_OUT, and STLN_OUT pins. When the slave mode is enabled, STFRM_OUT and
STLN_OUT become input pins.
The start and end of integration are controlled by EXPOSURE and STFRM_OUT pulses,
respectively. While a STFRM_OUT pulse is used to stop integration, it is also used to
enable the readout process.
After integration is stopped, the user provides STLN_OUT pulses to trigger row readout.
A full row of data is read out with each STLN_OUT pulse. The user must provide enough
time between successive STLN_OUT pulses to allow the complete readout of one row.
It is also important to provide additional STLN_OUT pulses to allow the sensors to read
the vertical blanking rows. It is recommended that the user program the vertical blank
register (R0x06) with a value of 4, and achieve additional vertical blanking between
frames by delaying the application of the STFRM_OUT pulse.
The elapsed time between the rising edge of STLN_OUT and the first valid pixel data is
calculated for context A by [horizontal blanking register (R0x05) + 4] clock cycles. For
context B, the time is (R0xCD + 4) clock cycles.
CONTROLLER
Aptina Confidential and Proprietary
FRAME_VALID
LINE_VALID
EXPOSURE
D
SYSCLK
PIXCLK
OUT
49
(9:0)
MT9V034: 1/3-Inch Wide-VGA Digital Image Sensor
xxx
MT9V034
Aptina Imaging reserves the right to change products or specifications without notice.
Exposure Time
©2008 Aptina Imaging Corporation. All rights reserved.
Feature Description
xxx
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