ws57c71c STMicroelectronics, ws57c71c Datasheet
ws57c71c
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ws57c71c Summary of contents
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... It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate EPROM cell. The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8 device. This RPROM is capable of operating at speeds as fast address access time, which enables used directly with today's fast microprocessors and DSP processors without introducing any wait states ...
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... WS57C71C ABSOLUTE MAXIMUM RATINGS* Storage Temperature............................–65° 150°C Voltage on any Pin with Respect to Ground ....................................–0.6V to +7V V with Respect to Ground...................–0. 13V PP ESD Protection .................................................. * NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of ...
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... CSX, CS2 OUTPUTS Over Operating Range. (See Above) 57C71C-35 57C71C-45 SYMBOL MIN MAX MIN t 35 ACC VALID t ACC t CS WS57C71C 57C71C-55 57C71C-70 MAX MIN MAX MIN MAX VALID t DF UNITS ns 2-57 ...
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... WS57C71C CAPACITANCE ( 25° MHz A SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT C V Capacitance VPP PP NOTES: 4. This parameter is only sampled and is not 100% tested. 5.Typical values are for T = 25°C and nominal supply voltages. A TEST LOAD (High Impedance Test Systems ...
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... SUPPLY VOLTAGE ( V ) NORMALIZED T aa vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 0.8 0.6 -55 -35 - AMBIENT TEMPERATURE ( °C ) TYPICAL ACCESS TIME CHANGE 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 6.0 0.0 NORMALIZED SUPPLY CURRENT 1.2 1.1 1.0 0.9 0.8 -55 -35 -15 85 105 125 WS57C71C vs. OUTPUT LOADING 200 400 600 800 1000 CAPACITANCE ( pF ) vs. AMBIENT TEMPERATURE 105 125 AMBIENT TEMPERATURE (°C) 2-59 ...
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... WS57C71C PROGRAMMING INFORMATION DC CHARACTERISTICS SYMBOLS Input Leakage Current Supply Current During Programming Pulse I V Supply Current CC CC Output Low Voltage During Verify mA) OL Output High Voltage During Verify –4 mA) OH NOTE must not be greater than 13 volts including overshoot. ...
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... WS57C71C-55TI 55 WS57C71C-55TMB 55 WS57C71C-70L 70 WS57C71C-70T 70 WS57C71C-70TMB 70 NOTE: 8. The actual part marking will not include the initials "WS." PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS The WS57C71C is programmed using Algorithm D shown on page 5-9. Return to Main Menu PACKAGE PACKAGE TYPE DRAWING 32 Pin PLDCC J4 32 Pin CLDCC L3 28 Pin CERDIP, 0.3" T2 ...