m54hc166k1 STMicroelectronics, m54hc166k1 Datasheet

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m54hc166k1

Manufacturer Part Number
m54hc166k1
Description
8 Bit Piso Shift Register
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
The M54HC166 is an high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated with silicon
gate C
It consists of parallel or serial inputs and a
serial-out 8 bit shift register with gated clock inputs
and an overriding clear input. The parallel-in or
serial-in modes are controlled by the SHIFT/LOAD
PIN CONNECTION
March 2004
HIGH SPEED:
f
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
WIDE OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 166
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9306-043
MAX
CC
PLH
OH
NIH
CC
2
=4 A(MAX.) at T
| = I
MOS technology.
(OPR) = 2V to 6V
= 63 MHz (TYP.) at V
= V
t
PHL
OL
NIL
= 4mA (MIN)
= 28% V
A
CC
=25°C
(MIN.)
CC
= 6V
RAD-HARD 8 BIT PISO SHIFT REGISTER
ORDER CODES
input. When the SHIFT/LOAD input is held high,
the serial data input is enabled and the eight
flip-flops perform serial shifting with each clock
pulse; when held low, the parallel data inputs are
enabled and synchronous loading occurs on the
next clock pulse. Clocking is accomplished on the
low-to-high level edge of the clock pulse. The
CLOCK-INHIBIT input should be changed to the
high only while the clock input is held high. A direct
clear input overrides all other inputs, including the
clock, and sets all flip-flops to zero. Functional
details are shown in the truth table and the timing
chart. All inputs are equipped with protection
circuits against static discharge and transient
excess voltage.
PACKAGE
DILC
FPC
DILC-16
M54HC166D
M54HC166K
FM
M54HC166
FPC-16
M54HC166D1
M54HC166K1
EM
1/11

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m54hc166k1 Summary of contents

Page 1

... Functional details are shown in the truth table and the timing chart. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M54HC166 DILC-16 FPC- M54HC166D M54HC166D1 M54HC166K M54HC166K1 1/11 ...

Page 2

M54HC166 IEC LOGIC SYMBOLS INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE SHIFT/ CLOCK CLEAR LOAD INH Don’t Care a........h : ...

Page 3

LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays TIMING CHART M54HC166 3/11 ...

Page 4

M54HC166 ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 5

DC SPECIFICATIONS Symbol Parameter V V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Quiescent Supply CC Current Test ...

Page 6

M54HC166 AC ELECTRICAL CHARACTERISTICS (C Symbol Parameter Output Transition TLH THL Time t t Propagation Delay PLH PHL Time (CLOCK - QH) t Propagation Delay PHL Time (CLEAR - QH) f Maximum Clock MAX Frequency t Minimum ...

Page 7

TEST CIRCUIT C = 50pF or equivalent (includes jig and probe capacitance pulse generator (typically OUT WAVEFORM 1: MINIMUM PULSE WIDTH (CLEAR), REMOVAL TIME (CLEAR TO CLOCK) (f=1MHz; 50% duty cycle) M54HC166 ...

Page 8

M54HC166 WAVEFORM 2: PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (CLOCK), SETUP AND HOLD TIME (SI to CLOCK) (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY TIME, SETUP AND HOLD TIME (PI, S/L to CLOCK) (f=1MHz; 50% duty cycle) 8/11 ...

Page 9

DILC-16 MECHANICAL DATA DIM. MIN. A 2.1 a1 3.00 a2 0.63 B 1.82 b 0.40 b1 0.20 0.254 D 20.06 20. 17.65 17.78 e3 7. 10.90 L 1.14 mm. TYP MAX. MIN. ...

Page 10

M54HC166 DIM. MIN. A 6.75 B 9.76 C 1.49 D 0.102 E 8. 0.38 H 6.0 L 18. 10/11 FPC-16 MECHANICAL DATA mm. TYP MAX. 6.91 7.06 9.94 10.14 1.95 0.127 ...

Page 11

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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