m54hc112k STMicroelectronics, m54hc112k Datasheet

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m54hc112k

Manufacturer Part Number
m54hc112k
Description
Dual J-k Flip Flop With Preset And Clear
Manufacturer
STMicroelectronics
Datasheet
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
DESCRIPTION
The M54HC112 is an high speed CMOS DUAL
J-K FLIP-FLOP WITH PRESET AND CLEAR
fabricated with silicon gate C
The
PIN CONNECTION
March 2004
HIGH SPEED:
f
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
WIDE OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 112
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9203-051
MAX
CC
PLH
OH
NIH
CC
M54HC112
=2 A(MAX.) at T
| = I
(OPR) = 2V to 6V
= 79MHz (TYP.) at V
= V
t
PHL
OL
NIL
= 4mA (MIN)
= 28% V
dual
A
CC
=25°C
JK
(MIN.)
CC
2
MOS technology.
flip-flop
= 6V
features
ORDER CODES
individual J, K, clock, and asynchronous set and
clear inputs for each flip-flop. When the clock goes
high, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs
may be allowed to change when the clock pulse is
high and the bistable will function as shown in the
truth table. Input data is transferred to the input on
the negative going edge of the clock pulse.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PACKAGE
DILC
FPC
DILC-16
M54HC112D
M54HC112K
FM
M54HC112
FPC-16
M54HC112D1
M54HC112K1
EM
1/11

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m54hc112k Summary of contents

Page 1

... Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped with protection circuits against static discharge and transient excess voltage. 2 MOS technology. flip-flop features M54HC112 DILC-16 FPC- M54HC112D M54HC112D1 M54HC112K M54HC112K1 1/11 ...

Page 2

M54HC112 IEC LOGIC SYMBOLS INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS CLR ...

Page 3

LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output ...

Page 4

M54HC112 DC SPECIFICATIONS Symbol Parameter V V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Quiescent Supply CC Current ...

Page 5

AC ELECTRICAL CHARACTERISTICS (C Symbol Parameter Output Transition TLH THL Time t t Propagation Delay PLH PHL Time ( Propagation Delay PLH PHL Time (CLR Maximum Clock ...

Page 6

M54HC112 TEST CIRCUIT C = 50pF or equivalent (includes jig and probe capacitance pulse generator (typically OUT WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CK), SETUP AND HOLD TIME (J to ...

Page 7

WAVEFORM 2: PROPAGATIONS DELAY TIME, MINIMUM PULSE WIDTH (CLR, PR) (f=1MHz; 50% duty cycle) WAVEFORM 3: MINIMUM REMOVAL TIME (CLR to CK) (f=1MHz; 50% duty cycle) M54HC112 7/11 ...

Page 8

M54HC112 WAVEFORM 4: MINIMUM REMOVAL TIME (PR to CK) (f=1MHz; 50% duty cycle) 8/11 ...

Page 9

DILC-16 MECHANICAL DATA DIM. MIN. A 2.1 a1 3.00 a2 0.63 B 1.82 b 0.40 b1 0.20 0.254 D 20.06 20. 17.65 17.78 e3 7. 10.90 L 1.14 mm. TYP MAX. MIN. ...

Page 10

M54HC112 DIM. MIN. A 6.75 B 9.76 C 1.49 D 0.102 E 8. 0.38 H 6.0 L 18. 10/11 FPC-16 MECHANICAL DATA mm. TYP MAX. 6.91 7.06 9.94 10.14 1.95 0.127 ...

Page 11

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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