adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 13

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

Table 2. Pin Function Description
Mnemonic
ACK
ADDR23–0
AGND
AV
BMS
BMSTR
BR6–1
BRST
CAS
CLK_CFG1–0
Rev. 0
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DD
Type
I/O/S
I/O/T
G
P
I/O/T
O
I/O/S
I/O/T
I/O/T
I
Function
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The SHARC Mel-100 deasserts ACK as an output to add wait states to a synchronous
access of its IOP registers. ACK has a 20 kΩ internal pull-up resistor that is enabled during reset or on DSPs
with ID2–0 = 00x.
External Bus Address. The SHARC Mel-100 outputs addresses for external memory and peripherals on these
pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the IOP registers of
other SHARC Mel-100 processors, while all other internal memory resources can be accessed indirectly via
DMA control (that is, accessing IOP DMA parameter registers). The SHARC Mel-100 inputs addresses when a
host processor or multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the
DSP’s ADDR23–0 pins maintains the input at the level to which it was last driven. This latch is only enabled on
the SHARC Mel-100 with ID2–0 = 00x.
Analog Power Supply Return.
Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock generator). This pin
has the same specifications as V
section.
Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins; see Table 3
on page 17. This input is a system configuration selection that should be hardwired. For Host and EPROM
boot, DMA Channel 10 (EPB0) is used. For Link boot and SPI boot, DMA Channel 8 is used. Three-state only in
EPROM boot mode (when BMS is an output).
Bus Master Output. In a multiprocessor system, indicates whether the SHARC Mel-100 is current bus master
of the shared external bus. The SHARC Mel-100 drives BMSTR high only while it is the bus master. In a single-
processor system (ID = 000), the processor drives this pin high.
Multiprocessing Bus Requests. Used by multiprocessing SHARC Mel-100 processors to arbitrate for bus
mastership. A SHARC Mel-100 only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and
monitors all others. In a multiprocessor system with less than six SHARC Mel-100 processors, the unused BRx
pins should be pulled high; the processor’s own BRx line must not be pulled high or low because it is an
output.
Sequential Burst Access. BRST is asserted by SHARC Mel-100 to indicate that data associated with
consecutive addresses is being read or written. A slave device samples the initial address and increments an
internal address counter after each transfer. The incremented address is not pipelined on the bus. A master
SHARC Mel-100 in a multiprocessor environment can read slave external port buffers (EPBx) using the burst
protocol. BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that,
except for the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on
the DSP’s BRST pin maintains the input at the level to which it was last driven. This latch is only enabled on
the SHARC Mel-100 with ID2–0 = 00x.
SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,
defines the operation for the SDRAM to perform.
Core/CLKIN Ratio Control. SHARC Mel-100 core clock (instruction cycle) rate is equal to n × PLLICLK where n
is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs. These pins can also be used in combination with
the CLKDBL pin to generate additional core clock rates of 6 × CLKIN and 8 × CLKIN (see the Clock Rate Ratios
table in the CLKDBL description).
DDINT
, except that added filtering circuitry is required. See the Power Supplies
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone]
ADSST-SHARC-Mel-100
© 2003 Analog Devices, Inc. All rights reserved.
SHARC
Audio Processor
®
www.analog.com
Mel-100