adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 21

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

POWER DISSIPATION
Total power dissipation has two components: one due to
internal circuitry and one due to the switching of external
output drivers. Internal power dissipation depends on the
instruction execution sequence and the data operands involved.
Using the current specifications (I
I
the programmer can estimate the SHARC Mel-100 processor’s
internal power supply (V
application, according to the following formula:
I
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on
and is calculated by
The load capacitance should include the processor package
capacitance (C
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/t
SDRAM memory.
Example:
Estimate P
The P
drive.A typical power consumption can now be calculated for
these conditions by adding a typical internal power dissipation:
where P
Electrical Characteristics (Table 5 on page 19).
DD-IDLE
DDINT
• The number of output pins that switch during each cycle
• The maximum frequency at which they can switch (f)
• Their load capacitance (C)
• Their voltage swing (V
• A system with one bank of external memory (32 bit)
• Two 1M × 16 SDRAM chips are used, each with a load
• External data memory writes can occur every cycle at a
• The bus cycle time is 50 MHz
• The external SDRAM clock rate is 100 MHz
• SDRAM refresh cycles are ignored
• Addresses are incremental and on the same page
P
EXT
EXT
) from the Electrical Characteristics (Table 5 on page 19),
(O)
of 10 pF (ignoring trace capacitance)
rate of 1/t
PLL
equation is calculated for each class of pins that can
= O × C × V
= % Peak × I
+ % High × I
+ % Low × I
+ % Idle × I
P
EXT
TOTAL
is AI
with the following assumptions:
IN
= P
DD
). The switching frequency includes driving the
CK
× 1.8 V, using the value for AI
, with 50% of the pins switching
EXT
DD-IDLE
DD
DD-INLOW
DD-INPEAK
DD-INHIGH
+ P
2
× f
DDINT
INT
+ P
) input current for a specific
DD
)
PLL
DD-INPEAK
CK
while writing to an
, I
DD-INHIGH
DD
listed in the
, I
DD-INLOW
Rev. 0 | Page 21 of 28
,
OUTPUT DRIVE CURRENTS
Figure 14 shows typical I-V characteristics for the output
drivers of the SHARC Mel-100. The curves represent the
current drive capability of the output drivers as a function of
output voltage.
TEST CONDITIONS
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time, t
the point when a reference signal reaches a high or low voltage
level to the point when the output has reached a specified high
or low trip point, as shown in Figure 15. If multiple pins (such
as the data bus) are enabled, the measurement value is that of
the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ∆V is dependent on the capacitive load, C
the load current, I
equation
The output disable time, t
and t
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. t
and with ∆V equal to 0.5 V.
t
DECAY
DECAY
–10
–20
–70
–30
–40
–50
–60
70
60
50
40
30
20
10
0
, as shown in Figure 15. The time t
0
V
=
DDEXT
C
V
0.5
DDEXT
L
I
L
= 3.47V, –40°C
Figure 14. Typical Drive Currents
. This decay time can be approximated by the
∆
L
V
DDEXT
V
DECAY
= 3.47V, –40°C
1.0
SOURCE (V
= 3.3V, +25°C
V
is calculated with test loads C
DIS
DDEXT
, is the difference between t
1.5
ADSST-SHARC-Mel-100
= 3.13V, +105°C
DDEXT
V
2.0
DDEXT
) VOLTAGE (V)
ENA
= 3.3V, +25°C
V
2.5
DDEXT
, is the interval from
MEASURED
= 3.13V, +105°C
3.0
3.5
is the
MEASURED
L
and I
L
4.0
, and
L
,