adsst-sharc-mel-100 Analog Devices, Inc., adsst-sharc-mel-100 Datasheet - Page 7

• Manufacturer Part Number: adsst-sharc-mel-100
• Description: Sharc Mel-100 Audio Processor
• Manufacturer: Analog Devices, Inc.

Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the SHARC Mel-100’s enhanced
Harvard architecture, enable unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15, and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The SHARC Mel-100 features an enhanced Harvard
architecture in which the data memory (DM) bus transfers data
and the program memory (PM) bus transfers both instructions
and data (see Figure 4). With the SHARC Mel-100’s separate
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and an instruction (from the cache), all within a
single cycle.
(HOST OR SLAVE)
COMPATIBLE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICES
CLOCK
(2 MAX)
SERIAL
DEVICE
SPI
SERIAL
DEVICE
SERIAL
DEVICE
SERIAL
DEVICE
LINK
12
3
2
IRQ2-0
D3A
D3B
CLKIN
XTAL
CLK_CFG1–0
CLKDBL
EBOOT
LBOOT
FLAG11–0
TIMEXP
RPBA
ID2-0
LXCLK
LXACK
LXDAT7–0
SCLK0
FS0
D0A
D0B
SCLK1
FS1
D1A
D1B
SCLK2
FS2
D2A
D2B
SCLK3
FS3
SPICLK
SPIDS
MOSI
MISO
RESET
ADSST SHARC
MEL-100
RSTOUT
DATA47–16
ADDR23–0
SDCLK1–0
DMAR1–2
DMAG1–2
CLKOUT
SDCKE
MS3–0
BR1–6
SDA10
SDWE
BRST
REDY
SBTS
JTAG
Figure 4. System Block Diagram
DQM
HBG
BMS
ACK
HBR
RAS
CAS
WR
RD
PA
CS
7
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Instruction Cache
The SHARC Mel-100 includes an on-chip instruction cache that
enables 3-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache enables full speed execution of core, looped operations
such as digital filter multiply-accumulates and FFT butterfly
processing.
Data Address Generators with Hardware Circular Buffers
The SHARC Mel-100 processor’s two data address generators
(DAGs) are used for indirect addressing and implementing
circular data buffers in hardware. Circular buffers enable
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
SHARC Mel-100 contain sufficient registers to enable the
creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
CS
DATA
ADDR
DATA
OE
WE
ACK
CS
DATA
DATA
ADDR
ADDR
PERIPHERALS
(OPTIONAL)
PROCESSOR
DMA DEVICE
(OPTIONAL)
(OPTIONAL)
INTERFACE
(OPTIONAL)
MEMORY
EPROM
AND
HOST
BOOT
DQM
RAS
CAS
WE
CLK
CKE
A10
CS
ADDR
DATA
ADSST-SHARC-Mel-100
(OPTIONAL)
SDRAM