m366s3253bts Samsung Semiconductor, Inc., m366s3253bts Datasheet - Page 7

• Manufacturer Part Number: m366s3253bts
• Description: 32mx64 Sdram Dimm Based On 32mx8, 4banks, 8k Refresh, 3.3v Synchronous Drams With Spd
• Manufacturer: Samsung Semiconductor, Inc.

AC OPERATING TEST CONDITIONS
M366S3253BTS
OPERATING AC PARAMETER
Notes :
(AC operating conditions unless otherwise noted)
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
(Fig. 1) DC output load circuit
and then rounding off to the next higher integer.
870
Parameter
Parameter
3.3V
1200
50pF
V
V
OH
OL
CAS latency=3
CAS latency=2
(DC) = 0.4V, I
(V
(DC) = 2.4V, I
DD
= 3.3V
t
t
t
t
t
t
t
t
t
RAS
RRD
RCD
t
CCD
Symbol
t
RAS
RDL
CDL
DAL
BDL
RC
RP
OL
OH
0.3V, T
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
= 2mA
= -2mA
A
= 0 to 70 C)
See Fig. 2
tr/tf = 1/1
2.4/0.4
tCC=7.5ns
Value
1.4
1.4
Output
15
20
20
45
65
2 CLK + 20 ns
PC133 Unbuffered DIMM
Version
100
-75
2
1
1
1
2
-
(Fig. 2) AC output load circuit
tCC=10ns
20
20
20
50
70
Z0 = 50
REV. 0.1 July. 2000
Unit
CLK
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ea
-
Vtt = 1.4V
Unit
50
ns
50pF
V
V
V
Note
1
1
1
1
1
2
2
2
3
4