k4r881869m Samsung Semiconductor, Inc., k4r881869m Datasheet - Page 46

• Manufacturer Part Number: k4r881869m
• Description: 288mbit Rdram 512k X 18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

K4R881869M
Electrical Conditions
Timing Conditions
Symbol
T
V
V
v
V
V
V
V
V
V
A
V
V
V
V
V
V
Symbol
t
t
t
t
t
t
t
t
CYCLE
CR
CH
TR
DCW
DR
S
DR1,
DD,N,
J
DD,
DD,N,
CMOS
TERM
REF
DIL
DIH
DIS
DI
X
CM
CIS,CTM
CIS,CFM
IL,CMOS
IH,CMOS
, t
, t
, t
, t
H
CF
CL
DF
t
V
DF1
v
DDA
V
DDA,N
DDA,N
Parameter
CTM and CFM cycle times (-600)
CTM and CFM cycle times (-711)
CTM and CFM cycle times (-800)
CTM and CFM input rise and fall times
CTM and CFM high and low times
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)
Domain crossing window
DQA/DQB/ROW/COL input rise/fall times
DQA/DQB/ROW/COL-to-CFM set/hold @ t
DQA/DQB/ROW/COL-to-CFM set/hold @ t
DQA/DQB/ROW/COL-to-CFM set/hold @ t
SIO0, SIO1 input rise and fall times
Parameter and Conditions
Junction temperature under bias
Supply voltage
Supply voltage droop (DC) during NAP interval (t
Supply voltage ripple (AC) during NAP interval (t
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
Termination voltage
Reference voltage
RSL data input - low voltage
RSL data input - high voltage
RSL data input swing: V
RSL data asymmetry: A
RSL clock input - crossing point of true and complement signals
RSL clock input - common mode V
RSL clock input swing: V
RSL clock input swing: V
CMOS input low voltage
CMOS input high voltage
DI
DIS
CIS
CIS
= [(V
= V
= V
= V
Table 18: Electrical Conditions
DIH
DIH
CIH
CIH
Table 19: Timing Conditions
CM
- V
- V
- V
- V
a
= (V
DIL
REF
CIL
CIL
) + (V
CIH
CYCLE
CYCLE
CYCLE
(CTM,CTMN pins).
(CFM,CFMN pins).
+V
Page 44
DIL
NLIMIT
NLIMIT
CIL)
=3.33ns
=2.81ns
=2.50ns
- V
/2
REF
)
)
)]/V
DIS
0.275
0.240
0.200
Min
3.33
2.80
2.50
40%
-0.1
0.2
0.0
0.9
0.2
-
b,d
c,d
d
V
CMOS
V
2.50 - 0.13
2.50 - 0.13
V
1.80 - 0.1
1.80 - 0.1
1.40 - 0.2
REF
REF
0.125
Min
0.35
- 0.3
-2.0
0.4
1.3
1.4
0
/2 + 0.25
-
-
+ 0.2
- 0.5
Max
60%
3.83
3.83
3.83
0.65
0.5
1.0
1.0
0.1
5.0
-
-
-
Preliminary
Direct RDRAM
Rev. 0.9 Jan. 2000
V
CMOS
V
2.50 + 0.13
2.50 + 0.25
V
V
1.80 + 0.2
1.80 + 0.1
1.40 + 0.2
t
t
t
CMOS
CYCLE
CYCLE
CYCLE
REF
REF
Unit
Max
0.70
0.70
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
2.0
2.0
1.0
-20
1.8
1.7
/2 - 0.25
+ 0.5
- 0.2
+0.3
Figure(s)
Figure 53
Figure 53
Figure 53
Figure 53
Figure 53
Figure 42
Figure 53
Figure 59
Figure 54
Figure 54
Figure 54
Figure 54
Figure 56
Unit
V
%
%
V
V
V
V
V
V
V
%
V
V
V
V
V
V
C
™