w66910 Winbond Electronics Corp America, w66910 Datasheet - Page 34

• Manufacturer Part Number: w66910
• Description: Te Mode Isdn S/t-controller With Microprocessor Interface
• Manufacturer: Winbond Electronics Corp America

7.6.1 D Channel Message Transfer Modes
The D channel HDLC controller operates in transparent mode.
Chracteristics:
Note. The LAPD protocol uses the CRC_ITU-T for Frame Check Sequence. The polynominal is X
For address recognition, the W66910 provides four programmable registers for individual SAPI and TEI values, SAP1-2 and
TEI1-2, plus two fixed values for group SAPI and TEI, SAPG and TEIG. The SAPG equals 02H(C/R=1) or 00H(C/R=0) which
corresponds to SAPI = 0. The TEIG equals FFH which corresponds to TEI = 127. Incoming frame with 1
or SAP2 or SAPG) and 2
being discarded and stuffed bits being removed.
The valid address combinations are :
The receive frame address comparisons can be disabled (masked) per bit basis by setting the D_SAM and D_TAM registers, but
comparisons with the SAPG or TEIG cannot be disabled.
7.6.2 Reception of Frames in D Channel
A 128-byte FIFO is provided in the receive direction. The data movement is handled by interrupts.
There are two interrupt sources: Receive Message Ready (D_RMR) and Receive Message End (D_RME). The D_RMR interrupt
indicates that at least 64 bytes of data have been received and the message/ frame is not ended. Upon D_RMR interrupt, the
-
-
-
-
-
-
-
-
-
-
-
-
Receive frame address recognition
Address comparison maskable bit-by-bit
Flag generation / deletion
Zero bit insertion/ deletion
Frame Check Sequence (FCS) generation/ check with CRC_ITU-T
SAP1 and TEI1
SAP1 and TEI=127
SAP2 and TEI2
SAP2 and TEI=127
SAPI=0 and TEI1
SAPI=0 and TEI2
SAPI=0 and TEI=127
nd
address octet= (TEI1 or TEI2 or TEIG) will be stored in the receive FIFO, with flag and FCS fields
-34 -
W66910 PCI ISDN S/T-Controller
Publication Release Date:
16
+ X
12
st
+ X
address octet= (SAP1
5
+ 1.
Data Sheet
Revision 1.0
Feb,2001