w66910 Winbond Electronics Corp America, w66910 Datasheet - Page 76
w66910
Manufacturer Part Number
w66910
Description
Te Mode Isdn S/t-controller With Microprocessor Interface
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W66910.pdf
(81 pages)
- Current page: 76 of 81
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Parameter
ta1
ta2
ta3
ta4
ta5
ta6
ta7
ta8
Note : The PCM clocks are locked to the S/T receive clock. At every two or three PCM frame time (125 s), PBCK and PFCK1,
PFCK2 may be adjusted by one local oscillator cycle (130 ns) in order to synchronize with S/T clock. This shift is made on the
LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1 and PFCK2 with
jitter amplitude 260 ns (peak-to-peak) and jitter frequency about 2.67~4 kHz.
9.4.2 8-bit Microprocessor Timing
Intel mode read cycle timing
AD<7:0>
CS#
ALE
RD#
Parameter Descriptions
PBCK pulse high
PBCK pulse low
Frame clock asserted from
PBCK
PTXD data delay from PBCK
Frame clock deasserted from
PBCK
PTXD hold time from PBCK
PRXD setup time to PBCK
PRXD hold time from PBCK
t1
t2
A<7:0>
t3
t4
t6
t8
t5
D<7:0>
Min.
195
10
20
10
t9
t7
t10
-76 -
Nominal
325
325
t11
Max.
455
20
20
20
A<7:0>
W66910 PCI ISDN S/T-Controller
Remarks
Unit = ns
Publication Release Date:
Data Sheet
Revision 1.0
Feb,2001
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