r8a66174sp Renesas Electronics Corporation., r8a66174sp Datasheet - Page 2

• Manufacturer Part Number: r8a66174sp
• Description: Parallel-in Serial-out Data Buffer With Fifo
• Manufacturer: Renesas Electronics Corporation.

R8A66174SP
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The information on data bus D0~D7 is loaded as command when C//D=1, and as data when C//D=0.
There are four kinds of commands.
(1) Command 1. Five kinds of division ratios of the clock input
(2) Command 2. R8A66174 is set as write mode. The CPU is capable of writing 8-bit parallel data of up to 63
(3) Command 3. R8A66174 is set as serial output mode. All data written in the internal memory (FIFO) is
(4) Command 4. cancels the /INT and sets/resets the two control ports (LATCH, /OE).
FUNCTION TABLE
REJ03F0278-0101 Rev.1.01 Oct.06.2008
Page 2 of 11
Note1 *1 : The same operation as *3 and *4 in the SERIAL OUT mode. The output is not changed in other modes.
COMMAND/
DATA INPUT
CHIP SELECT
INPUT
WRITE INPUT
CLOCK INPUT
INTERRUPT
REQUEST
OUTPUT
－
－
RESET
INPUT
bytes into the internal memory (FIFO) of the R8A66174.
outputted as serial data in sync with the shift clock which is set by command 1. Then, each data is
outputted from LSB. When all stored data has outputted, R8A66174 will output the interrupt request /INT
to CPU.
After command4, if command3 is executed immediately, the data which is already written will be re-outpu-
tted.
1
2
3
4
DATA BUS
*2 : The output is not changed.
*3 : The Φ division pulse which is set by command 1 is outputted on /WR rise.
*4 : SDATA (n) is output on SCLK fall (n-1).
*5 : Indicates 1 when /WR is 0, don't care when /WR is 1.
X : Don't care
/R
0
1
1
Control inputs
/CS C//D /WR D7
RESET
* 5
* 5
×
1
0
0
C/D
WR
INT
CS
D0
D1
D2
D3
D4
D5
D6
D7
Φ
×
×
1
1
0
1
×
×
1
19
18
16
17
11
1
2
3
4
5
6
7
8
9
×
×
×
×
8
×
×
1
1
1
1
1
0
×
0
×
×
0
CONTROL
CIRCUIT
INPUT
SELECTOR
COMMAND REGISTER
D6
×
×
0
0
0
0
1
×
×
×
×
×
×
Input
CK
D5
DIVIDER
×
×
×
×
×
×
×
×
0
0
1
1
0
Data inputs
D4
×
×
0
1
0
1
0
×
×
×
×
×
×
WR
CK
S
D3
×
×
×
0
×
0
×
×
1
COUNTER
WRITE
RD
D2
D2
×
×
×
×
×
×
×
×
F/F GATE
SELECTOR
DECODER
63 X 8-BIT
D1
D1
×
×
×
×
×
×
×
×
SRAM
D0
×
×
×
×
×
×
×
0
1
SCLK SDATA /INT
COUNTER
RD
* 1
* 3
* 3
0
0
0
0
0
0
0
0
0
0
READ
CONVERTER
BIT/BYTE
* 1
* 4
* 4
0
0
0
0
0
0
0
0
0
0
Outputs
* 1
1
1
1
1
1
1
1
1
1
1
0
1
CK
are set up.
LOAD
/OE LATCH
* 2
D2
CK
1
REGISTER
* 2
D1
DETECTION
0
MATCHING
SHIFT
8-BIT
CIRCUIT
Initialize
Memory contents not changed
Φ
1/2 division of Φ
1/4 division of Φ
1/8 division of Φ
1/16 division of Φ
WRITE MODE setting
WRITE operation
SERIAL OUT MODE setting
SERIAL OUT
SERIAL OUT end
set/reset the /OE and LATCH, cancel /INT
13
12
14
15
Remark
SDATA
SCLK
LATCH
OE
Valid when D7 is
high-level
WRITE MODE
SERI. OUT
MODE
SHIFT CLOCK
OUTPUT
LATCH OUTPUT
OUTPUT ENABLE
OUTPUT
SHIFT DATA
OUTPUT