h5ps2g43mfp Hynix Semiconductor, h5ps2g43mfp Datasheet
h5ps2g43mfp
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h5ps2g43mfp Summary of contents
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... DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP H5PS2G43MFP H5PS2G83MFP 1 ...
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... Revision Details Rev. 0.1 Initial data sheet released 0.2 Corrected Typos & Ball out 0.3 Adjusted IDD Values Rev. 0.3 / May 2008 History H5PS2G43MFP H5PS2G83MFP Draft Date Jun. 2007 Aug. 2007 May. 2008 2 ...
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... Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC Output Parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP 3 ...
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... JEDEC standard 60ball FBGA(x4/x8) • Full strength driver option controlled by EMR • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Read Data Strobe supported (x8 only) • Self-Refresh High Temperature Entry Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP 4 ...
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... Operating Frequency table for complete part number. Hynix lead-free products are compliant to RoHS. Operating Frequency Grade tCK(ns 3. 2.5 S5 2.5 Rev. 0.3 / May 2008 Configuration Package 512Mx4 60 Ball 256Mx8 CL tRCD H5PS2G43MFP H5PS2G83MFP tRP Unit Clk 3 Clk 4 Clk 5 Clk 6 Clk 5 5 ...
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... VSS VDDQ C DQ3 D E VSS BA1 A14 ITEMS # of Bank Page size H5PS2G43MFP H5PS2G83MFP VSSQ DQS VDDQ DQS VSSQ NC VDDQ DQ0 VDDQ DQ2 VSSQ NC VSSDL CK VDD RAS CK ODT CAS VDD A6 A4 A11 ...
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... A DM/RDQS B VDDQ C DQ3 D E VSS BA1 A14 ITEMS # of Bank BA0, BA1, BA2 Page size H5PS2G43MFP H5PS2G83MFP VSSQ DQS VDDQ DQS VSSQ DQ7 VDDQ DQ0 VDDQ DQ2 VSSQ DQ5 VSSDL CK VDD RAS CK ODT CAS VDD ...
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... LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMR(1) x4 DQS x8 DQS x8 DQS, RDQS, x16 LDQS and UDQS H5PS2G43MFP H5PS2G83MFP DESCRIPTION has become stable during the power on and initialization if EMR(1)[A11 EMR(1)[A11 EMR(1)[A11 ...
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... TYPE NC V Supply DDQ VSSQ Supply V Supply DDL V Supply SSDL VDD Supply V Supply SS V Supply REF Rev. 0.3 / May 2008 No Connect : No internal electrical connection is present. DQ Power Supply : 1.8V +/- 0.1V DQ Ground DLL Power Supply : 1.8V +/- 0.1V DLL Ground Power Supply : 1.8V +/- 0.1V Ground Reference voltage. H5PS2G43MFP H5PS2G83MFP -Continued- DESCRIPTION 9 ...
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... Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measure- ment conditions, please refer to JESD51-2 standard 85~95° Double refresh rate(tREFI: 3.9us) is required, and to enter the self refresh mode at this tem- OPER perature range, an EMR command is required to change internal refresh rate. Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP Rating Units - ...
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... V (ac) to test pin separately, then measure current I (ac), and VDDQ values defined in SSTL_18 IL V (ac (ac Rtt(eff) = I(V (ac delta 100% VDDQ H5PS2G43MFP H5PS2G83MFP Units Max. 1.9 V 1.9 V 1.9 V 0.51*VDDQ mV VREF+0.04 V MIN NOM MAX UNITS NOTES ohm 120 ...
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... Min. VREF + 0.125 - 0.3 DDR2 400,533 Min. Max. Min. - VREF + 0.200 - VREF - 0.250 Condition to V max for falling edges as shown in the figure below. IL(ac) delta TR max IL(ac) Rising Slew = H5PS2G43MFP H5PS2G83MFP Max. Units VDDQ + 0.3 V VREF - 0.125 V DDR2 667,800 Units Max VREF - 0.200 V Value Units 0 ...
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... VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. Rev. 0.3 / May 2008 Min. 0.5 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V DDQ SSQ < Differential signal levels > Min. 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 H5PS2G43MFP H5PS2G83MFP Max. Units Notes VDDQ + 0 Crossing point Max. Units Notes ...
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... V OUT DDQ OH /I must be less than 21 ohm for values of V OUT OL TT are based on the conditions given in Notes 1 and 2. They are used to test min plus a noise margin and V IH H5PS2G43MFP H5PS2G83MFP SSTL_18 Class II Units 0 DDQ SSTl_18 Units - 13.4 mA 13.4 ...
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... DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Rev. 0.3 / May 2008 Parameter Min - 0 0 Sout 1.5 VTT 25 ohms Reference point H5PS2G43MFP H5PS2G83MFP Nom Max Unit Notes - - ohms 1 1.5 ohms 6 4 ohms ...
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... IDD3P S 18 IDD3N 55 IDD4W 150 IDD4R 170 IDD5 230 Normal 8 IDD6 Low 7 power IDD7 295 Rev. 0.3 / May 2008 DDR2 800 x16 x4/x8 x16 - 100 - - 150 - - 170 - - 230 - - 295 - H5PS2G43MFP H5PS2G83MFP Units ...
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... RCD = 1* t CK(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions Rev. 0.3 / May 2008 Conditions Fast PDN Exit MR(12 Slow PDN Exit MR(12 H5PS2G43MFP H5PS2G83MFP Units ...
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... SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP 18 ...
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... H5PS2G43MFP H5PS2G83MFP DDR2- DDR2- 533 400 4-4-4 3-3-3 Units 4 3 tCK 7 70000 70000 ...
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... Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Rev. 0.3 / May 2008 DDR2 400 DDR2 667 DDR2 533 Symbol Min Max Min CCK 1.0 2.0 1.0 CDCK x 0. 1.0 2.0 1.0 CDI x 0.25 x CIO 2.5 4.0 2.5 CDIO x 0.5 x H5PS2G43MFP H5PS2G83MFP DDR2 800 Units Max Min Max 2.0 1.0 2.0 pF 0.25 x 0.25 pF 2.0 1.0 1.75 pF 0.25 x 0.25 pF 3.5 2.5 3.5 pF 0 ...
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... T ≤ 85℃ 7.8 CASE ≤ 95℃ 3.9 85℃＜ T CASE DDR2-667 min min min 6-6-6 4-4-4 5-5 H5PS2G43MFP H5PS2G83MFP 2Gb 4Gb Units Notes 105 127.5 195 327.5 ns 7.8 7.8 7.8 7.8 us 3.9 3.9 3.9 3.9 us DDR2-533 DDR2-400 Units Notes min min 4-4-4 3-3 tCK 15 15 ...
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... 0.25 tDQSH 0.35 - tDQSL 0.35 - tDSS 0.2 - tDSH 0.2 - tMRD 2 - tWPRE 0.35 - tWPST 0.4 0.6 tIS 350 - tIH 475 - tRPRE 0.9 1.1 tRPST 0.4 0.6 tRRD 7.5 - tRRD 10 - H5PS2G43MFP H5PS2G83MFP DDR2-533 Unit Note min max -500 +500 ps -450 +450 ps 0.45 0.55 tCK 0.45 0.55 tCK min(tCL 11,12 tCH) 3750 8000 ps 6,7,8,20 100 - ps 6,7,8,21 225 - ps - 6,7,8,25 - 6,7,8,26 0.6 - tCK 0 ...
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... C(max)+1 tANPD 3 tAXPD 8 tOIT 0 12 tIS+tCK+tI tDelay H H5PS2G43MFP H5PS2G83MFP -Continued- DDR2-533 Units Notes min max 37 tCK WR+tRP* - tCK 7 7.5 ns tRFC + 10 ns 200 - tCK ...
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... H5PS2G43MFP H5PS2G83MFP (DDR2-667 and DDR2-800) DDR2-800 Unit min max -400 +400 ps -350 +350 ps 0.48 0.52 tCK(av g) 0.48 0.52 tCK(av g) min(tCL(ab s tCH(abs)) 2500 8000 ps 6,7,8,20,28 6,7,8,21,28, 125 - ps tCK(av 0.6 ...
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... H5PS2G43MFP H5PS2G83MFP -Continued- DDR2-800 Unit Notes min max 7 24,32 7.5 ns 3,32 tRFC + 10 ns 200 - nCK 2 - nCK 2 nCK nCK 3 nCK 2 2 nCK ...
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... Output slew rate is characterized under the test conditions as shown below. VDDQ DUT Rev. 0.3 / May 2008 DQ DQS Output DQS RDQS Timing RDQS 25 reference point AC Timing Reference Load DQ Output DQS, DQS RDQS, RDQS 25 Test point Slew Rate Test Load H5PS2G43MFP H5PS2G83MFP DDQ Ω DDQ Ω 26 ...
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... (ac (ac) IH DMin DMin V (ac) IL Figure -- Data input (write) timing RPRE Q t DQSQmax t QH Figure -- Data output (read) timing H5PS2G43MFP H5PS2G83MFP t WPST V (dc (dc (dc) IH DMin DMin V (dc RPST ...
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... H5PS2G43MFP H5PS2G83MFP 1.4 V/ns 1.2 V/ns 1.0 V/ns △ △ △ △ △ △ tDH tDS tDH tDS tDH tDS - - - - - - - - - - - - - -59 -31 -47 -19 ...
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... H5PS2G43MFP H5PS2G83MFP 1.4 V/ns 1.2 V/ns 1.0 V/ns △ △ △ △ △ △ tDH tDS tDH tDS tDH tDS - - - - - - - - - - - - - -27 -29 - -44 -43 -62 -60 -86 - -67 -61 -85 -78 -109 -108 -152 -96 -85 -114 -102 -138 -132 -181 -183 -248 ...
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... Delta TF V Setup Slew Rate = Falling Signal Rev. 0.3 / May 2008 nominal slew rate Delta TR (dc)-V (ac)max Setup Slew Rate REF IL Rising Signal Delta TF H5PS2G43MFP H5PS2G83MFP nominal slew rate REF region V (ac)min-V (dc) REF IH = Delta TR 30 ...
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... Tangent line[V = Falling Signal Rev. 0.3 / May 2008 nominal line Tangent line Delta TR Setup Slew Rate Tangent line[V = Rising Signal (dc)-V (ac)max] REF IL Delta TF H5PS2G43MFP H5PS2G83MFP tangent line REF region (ac)min-V (dc)] REF IH Delta TR 31 ...
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... Hold Slew Rate V = Rising Signal Rev. 0.3 / May 2008 REF nominal slew rate Delta TR (dc)-V (dc)max Hold Slew Rate REF IL Falling Signal Delta TR H5PS2G43MFP H5PS2G83MFP nominal slew rate Delta TF V (dc)min - V (dc) IH REF = Delta TF 32 ...
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... Tangent line[V = Rising Signal Rev. 0.3 / May 2008 Tangent nominal line line Delta TR (dc)-V (ac)max] REF IL Delta TR Hold Slew Rate = Falling Signal H5PS2G43MFP H5PS2G83MFP nominal line tangent line Delta TF Tangent line[V (ac)min-V (dc)] REF IH Delta TF 33 ...
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... H5PS2G43MFP H5PS2G83MFP 1.0 V/ns △ tIH Uni ts Note s +154 ps 1 +149 ps 1 +143 ps 1 +135 ps 1 +105 ...
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... Hold(tIH) nominal slew rate for a falling signal is defined as the REF (dc). If the actual signal is always later than the nominal slew rate REF (dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual H5PS2G43MFP H5PS2G83MFP 1.0 V/ns △ tIS △ tIH ...
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... Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measure- ment points are not critical as long as the calculation is consistenet. Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP 36 ...
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... VTT + xmV VOL + 1xmV VTT -xmV VOL + 2xmV VTT - 2xmV tLZ , tRPRE begin point = 2*T1-T2 (ac) level to the differential data strobe crosspoint for a falling signal IL Differential Input waveform timing tDS tDH tDS tDH H5PS2G43MFP H5PS2G83MFP tLZ tRPRE begin point DDQ V min IH(ac) V min ...
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... For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP (ac) level for a rising sig- IH ...
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... H5PS2G43MFP H5PS2G83MFP DDR2-800 Units Notes min max -100 100 -200 200 ps 35 -160 160 ps ...
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... Rev. 0.3 / May 2008 Symbol min tCK(abs) tCK(avg),min+tJIT(per),min tCH(avg),min*tCK(avg),min+tJIT( tCH(abs) per),min tCL(avg),min*tCK(avg),min+tJIT( tCL(abs) per),min H5PS2G43MFP H5PS2G83MFP max Units tCK(avg),max+tJIT(per),max ps tCH(avg),max*tCK(avg),max+tJI ps T(per),max tCL(avg),max*tCK(avg),max+tJI ps T(per),max ...
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... DRAM input with respect to 0.5. For example input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtract- ing 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP 41 ...
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... However tAC values used in the equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated tJIT(duty),min - tERR(6-10per),min } Rev. 0.3 / May 2008 H5PS2G43MFP H5PS2G83MFP 42 ...
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... Fine Pitch Ball Grid Array Outline A1 CORNER 12.00 ± 0.10 INDEX AREA (2.50) <Top View> 8.00X8=6.40 2.10 ± 0.10 0. 63Xφ0.40 ± 0.05 <BALL View> Rev. 0.3 / May 2008 2.80 ± 0. BALL MARK 1.60 1.60 H5PS2G43MFP H5PS2G83MFP 4-R0.13MAX <SIDE View> 1.10 0.10 ± 0.34 ± 0.05 Note: All Dimensions are in millimeters. 43 ...