89ttm552 Integrated Device Technology, 89ttm552 Datasheet

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... It has congestion management mechanisms that manage shared traffic buffering resources. If buffer memory approaches its limit because data arrives at a queue faster than it can depart, the 89TTM552 performs per-queue congestion management. It can also intelligently discard lower priority traffic as it arrives until memory resources become available ...

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... Note: In the following 2 modes 1024 channels or output queues are supported. – NPF Streaming Interface (NPE-Fabric anticipated that this mode will be used on 89TTM552’s interface to a switch fabric. – CSIX over LVDS anticipated that this mode will be used to interface to a switch fabric (including the 89TSF552/89TSF500 fabric) ...

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... IDT 89TTM552 integrated AAL-5 SAR and DMA engine for data insertion and extraction. – Four classes of service. – Integrated AAL-5-compliant and packet-based SAR. – Programmable service rate. – Programmable queue thresholds. – Use of descriptors and DMA support for maximum performance. ...

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... IDT 89TTM552 9TTM55x 9TTM55x 9TTM55x iagra 9TTM55x iagrams iagra iagra Data Buffer Memory (DDR SDRAM) 89TTM552 Engine (DFC) SPI-4 Streaming DSR, Interface BRX or SIX-over-LVDS Forwarding and Thresholding Engine (AC) 89TTM553 Forwarding and Thresholding Engine (AC) Ingress (from PHY) ...

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... HSTL Class 1 PP_VREF The 89TTM552 operates the BRx and BTX interfaces with LVDS. The flexible interface can operates in either SPI-4.2, CSIX-over-LVDS, or NPF SI modes. The NPU/system receive interface has 16-bit data, 4-bit status for LVDS and 2-bit status for LVTTL. Signal Name ...

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... IDT 89TTM552 Signal Name RX_STAT_SOFP, RX_STAT_SOFN RX_STAT_DP[3:0], RX_STAT_DN[3:0] RX_STAT_PRTYP, RX_STAT_PRTYN RX_SPI4_STAT_CLK 3.3V LVTTL, 16mA RX_SPI4_STAT_D[1:0] 3.3V LVTTL, 16mA RX_VREF[1:0] 1. Note that the PIC buffer interface requires a 2.6V power supply. That means, separate power supplies are needed for the NPU/System Rx & Tx (LVDS) interfaces and the PIC buffer (SSTL2) interface. ...

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... IDT 89TTM552 Signal Name LLST_CLK_CP (C), 1.5V HSTL Class 1 LLST_CLK_CN (C#) LLST_CLK_KP (K), 1.5V HSTL Class 1 LLST_CLK_KN (K#) LLST_ADDR[21:0] 1.5V HSTL Class 1 LLST_RD_N 1.5V HSTL Class 1 LLST_WR_N 1.5V HSTL Class 1 LLST_DIN[17:0] 1.5V HSTL Class 1 LLST_DOUT[17:0] 1.5V HSTL Class 1 LLST_VREF[1:0] Signal Name MC_CLK_CP (C), 1.5V HSTL Class 1 MC_CLK_CN (C#) MC_CLK_KP (K), 1.5V HSTL Class 1 MC_CLK_KN (K#) MC_ADDR[21:0] 1.5V HSTL Class 1 MC_RD_N 1 ...

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... IDT 89TTM552 Signal Name MC_DOUT[17:0] 1.5V HSTL Class 1 MC_BW_N[1:0] 1.5V HSTL Class 1 MC_VREF[1:0] Signal Name SAR_CLK_CP (C), 1.5V HSTL Class 1 SAR_CLK_CN (C#) SAR_CLK_KP (K), 1.5V HSTL Class 1 SAR_CLK_KN (K#) SAR_ADDR[21:0] 1.5V HSTL Class 1 SAR_RD_N 1.5V HSTL Class 1 SAR_WR_N 1.5V HSTL Class 1 SAR_DIN[8:0] 1.5V HSTL Class 1 SAR_DOUT[8:0] 1.5V HSTL Class 1 SAR_VREF Signal Name DRAM_CLKP[2:0] 2.6V SSTL2 CMOS DRAM_CLKN[2:0] 2 ...

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... IDT 89TTM552 Signal Name DRAM0_CKE 2.6V SSTL2 CMOS DRAM0_CS_N 2.6V SSTL2 CMOS DRAM0_D[71:0] 2.6V SSTL2 CMOS DDAM0_DQS[8:0] 2.6V SSTL2 CMOS DRAM0_RAS_N 2.6V SSTL2 CMOS DRAM0_WE_N 2.6V SSTL2 CMOS DRAM1_ADDR[12:0] 2.6V SSTL2 CMOS DRAM1_BNK[1:0] 2.6V SSTL2 CMOS DRAM1_CAS_N 2.6V SSTL2 CMOS DRAM1_CKE 2.6V SSTL2 CMOS DRAM1_CS_N 2.6V SSTL2 CMOS DRAM1_D[71:0] 2.6V SSTL2 CMOS DDAM1_DQS[8:0] 2 ...

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... IDT 89TTM552 Signal Name ZBUS_CLK no internal pullup ZBUS_GNT_N 100K internal pullup ZBUS_DEVID[4:0] 100K internal pullup ZBUS_INT_N[2:0] 3.3V drive ZBUS_DIR 3.3V drive ZBUS_REQ_N 3.3V drive ZBUS_AD[31:0] 100K internal pullup ZBUS_PRTY[1:0] 100K internal pullup ZBUS_AVALID_N 100K internal pullup ZBUS_DVALID_N 100K internal pullup Signal Name ...

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... Async Chip reset input (active low) 3.3V, I N/A IDDQ input (active low). Attach to a 4.7K resistor to 3.3V. O 175/2 MHz 89TTM552 to 89TSF502 “turbo mode” interface O 175/2 MHz Source-synchronous turbo mode clock to the 89TSF502 — P — 1.5V I/O power for HSTL-2 I/Os: Isolated output buffer supply set nominally to 1.5V ...

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... PLL_SYS_VSSA PLL_SYS_VDDA PLL_SYS_VDD 89TTM552 Electrical Specifications 89TTM552 Electrical Specifications 89TTM552 Electrical Specifications 89TTM552 Electrical Specifications Some data are TBD and will be published as they become available. The specifications are subject to change without notice. Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings The absolute maximum ratings are the maximum conditions that the device can withstand without sustaining permanent damage ...

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... IDT 89TTM552 Operating Ranges Operating Ranges Operating Ranges Operating Ranges Symbol T Operating junction temperature range J I Input current for 1.5V power supply V15 I Input current for 1.8V power supply V18 I Input current for 2.5V power supply V25 I Input current for 2.6V power supply V26 I Input current for 3.3V power supply ...

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... IDT 89TTM552 Symbol Parameter V (3.3v LVTTL) Input low voltage for 3.3V LVTTL inputs IL33 V (3.3v LVTTL) Input high voltage for 3.3V LVTTL inputs IH33 V Output low voltage for 1.5V HSTL outputs OLHSTL V Output high voltage for 1.5V HSTL out- OHHSTL puts (VDDQ = 1.5V) V Output low voltage for 2.5V SSTL/CMOS ...

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... IDT 89TTM552 Symbol V Output voltage low Output differential voltage OD V Output offset voltage OS |DV | Change Change Output current Output current SAB the ground potential difference between the transmitter and the receiver GPD AC Characteristics AC Characteristics ...

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... IDT 89TTM552 Symbol T Statistics clock to output valid SCQV T Statistics clock to output invalid SCQX 1. The parameter is specified at 89TTM55x core clock frequency of 175 MHz. Symbol T DDR clock to address/control valid DCAV T DDR clock to address/control invalid DCAX T DDR clock to DQS transition DCQST T DDR clock to DQS Low-Z ...

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... IDT 89TTM552 Symbol f Status channel clock frequency S D Status clock duty percentage COC t Status clock to output data skew SKEW t Status channel input setup time SSCLK t Status channel input hold time HSCLK 1. Clock-data alignment is selectable in 1/4 cycle steps; skew is relative to this alignment Symbol ...

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... ---------------------- Ø Ø Parameter Table 25 89TTM552 Thermal Characteristics Ø (dissipated through board) Device T J Total Power = W W1 Ø Ø Figure 4 89TTM552 Thermal Circuit and numbers. The number comes from the heat sink manufacturer and depends on type of heat Ø ...

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... Reset Sequence 9TTM552 Reset Sequence A PLL reset sequence must be followed when resetting the 89TTM552 to ensure that clocks are stable when the chip comes out of reset. This section describes the reset sequence for the 89TTM552 device. The 89TTM552 uses data presented on the ZBus data and parity pins to determine the clock frequencies when the chip is in reset. The PLL_CFG_OVR pin controls this feature ...

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... IDT 89TTM552 ZB_PRTY[1:0] = 0x3, must be driven “HIGH” for the entire reset sequence cycles ZB_AD[31:0] = bits are set as: bit[12:0] = 0x154F = 0x1527 = 0x153a = 0x1526 = 0x1538 = 0x1525 = bit[21:13] = 0x080 = 0x060 = 0x1C0 = 0x1A0 = 0x180 = 0x160 = bit[30:22] = 0x080 = 0x060 = 0x1C0 = 0x1A0 = 0x180 = 0x160 = bit[31] = 0x1, keep “HIGH” for entire cycles Core/system clock frequency 187 ...

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... PLL_RX_LCK PLL_TX_LCK NOTE: - ZBUS_AD[ ] and ZBUS_PRTY[ ] are used to configure the chip operating frequency, and is listed on next page Pin List I/O Description Pin List I/O Description Pin List I/O Description Pin List I/O Description The 89TTM552 Pin List on page 22 uses the following I/O notations ...

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... IDT 89TTM552 9TTM552 Pin List 9TTM552 Pin List 9TTM552 Pin List 9TTM552 Pin List Pin Signal Type A2 FLQS_DIN12 I A3 FLQS_DIN05 I A4 FLQS_DIN09 I A5 STAT_DEP09 O A6 STAT_DEP06 O A7 SAR_DIN08 I A8 SAR_DIN05 I A9 SAR_DIN02 I A10 SAR_DOUT08 O A11 SAR_DOUT05 O A12 SAR_DOUT01 O A13 ...

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... IDT 89TTM552 Pin Signal Type C13 SAR_DOUT02 O C14 SAR_CLK_KN O C15 SAR_ADDR20 O C16 SAR_ADDR21 O C17 SAR_ADDR14 O C18 SAR_ADDR12 O C19 SAR_ADDR06 O C20 SAR_ADDR05 O C21 SAR_ADDR01 O C22 GND P C23 GND P C24 VDD15 P C25 VDD15 P C26 VDD33(VDDP) P C27 VDD15 P C28 VDD15 P C29 VDD15 P C30 VDD33(VDDP) ...

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... IDT 89TTM552 Pin Signal Type E25 PP_VREF P E26 PP_D I E27 PP_CLK I E28 MC_CLK_KP O E29 MC_DOUT15 O E30 MC_DOUT12 O E31 MC_DOUT06 O E32 MC_DOUT04 O E33 MC_BW_N1 O E34 GND P E35 GND P E36 MC_ADDR07 O E37 MC_ADDR03 O F1 FLQS_DIN20 I F2 FLQS_DIN21 I F3 FLQS_VREF1 P F4 VDD15 P F5 STAT_ARR16 ...

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... IDT 89TTM552 Pin Signal Type G37 MC_DIN17 I H1 FLQS_DOUT14 O H2 FLQS_DOUT13 O H3 FLQS_DOUT15 O H4 GND P H5 STAT_CLK O H6 FLQS_DIN07 I H7 STAT_ARR12 O H8 STAT_ARR08 O H9 STAT_ARR06 O H10 LLST_DIN15 I H11 STAT_ARR05 O H12 STAT_ARR03 O H13 LLST_RD_N O H14 SAR_CLK_CP I H15 LLST_DIN03 I H16 LLST_DIN01 I H17 LLST_DOUT14 ...

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... IDT 89TTM552 Pin Signal Type K12 VDD18 P K13 VDD18 P K14 VDD18 P K15 VDD18 P K16 VDD18 P K17 VDD18 P K18 GND P K19 ZBUS_DEVID02 I K20 ZBUS_DEVID00 I K21 ZBUS_DVALID_N B K22 ZBUS_AD30 B K23 ZBUS_AD22 B K24 ZBUS_AD26 B K25 ZBUS_AD20 B K26 ZBUS_AD14 B K27 ZBUS_AD15 B K28 ZBUS_AD11 B K29 ZBUS_AD07 ...

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... IDT 89TTM552 Pin Signal Type M30 ZBUS_AD01 B M31 GND P M32 SCAN_MODE_N I M33 MC_VREF0 P M34 GND P M35 MC_DIN05 I M36 MC_DIN03 I M37 MC_DIN02 I N1 TX_STAT_DN03 I N2 TX_STAT_SOFN I N3 TX_STAT_SOFP I N4 VDD33(VDDP FLQS_DOUT12 O N6 STAT_DEP02 O N7 TURBO_DATA03 O N8 TURBO_DATA02 O N9 GND P N10 VDD18 ...

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... IDT 89TTM552 Pin Signal Type T17 VDD18 P T18 VDD18 P T19 VDD18 P T20 VDD18 P T21 VDD18 P T22 VDD18 P T27 VDD33 P T28 VDD18 P T29 ZBUS_AD03 B T30 ZBUS_AD09 B T31 PLL_DDR_BYPCLK I T32 RX_SPI4_STAT_D01 O T33 RX_SPI4_STAT_D00 O T34 RX_VREF1 P T35 RX_STAT_DN02 O T36 RX_STAT_DP02 O T37 RX_STAT_DN03 O U1 TX_SOFN ...

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... IDT 89TTM552 Pin Signal Type W19 GND P W20 GND P W21 GND P W22 GND P W28 VDDO_25V_LVDS_DSR P W29 ZBUS_AD21 B W30 ZBUS_AD16 B W31 VDD33 P W32 VDD33 P W33 GND P W34 VDDO_25V_LVDS_DSR P W35 RX_STAT_PRTYN O W36 RX_STAT_PRTYP O W37 RX_SOFN I Y1 TX_DN13 O Y2 TX_DN12 O Y3 TX_DP12 O Y4 GND ...

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... IDT 89TTM552 Pin Signal Type AB21 VDD18 P AB22 VDD18 P AB27 PLL_RX_VDD P AB28 GND P AB29 VDD26 P AB30 VDD18 P AB31 VDD18 P AB32 GND P AB33 VDD18 B AB34 VDD18 P AB35 RX_DN12 I AB36 RX_DP12 I AB37 RX_DP13 I AC1 TX_CLKN O AC2 TX_DP08 O AC3 TX_DN08 O AC4 TX_VREF1 P AC5 TX_VREF ...

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... IDT 89TTM552 Pin Signal Type AF8 VDD26 P AF9 VDD26 P AF10 GND P AF11 VDD18 P AF27 VDD18 P AF28 GND P AF29 VDD26 P AF30 VDD26 P AF31 VDD18 P AF32 GND P AF33 VDD26 P AF34 VDD26 P AF35 RX_DP07 I AF36 RX_DN07 I AF37 RX_CLKN I AG1 TX_DP02 O AG2 TX_DN03 O AG3 TX_DP03 ...

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... IDT 89TTM552 Pin Signal Type AJ1 TX_PRTYP O AJ2 TX_DP00 O AJ3 TX_DN00 O AJ4 VDD26 P AJ5 DRAM0_RAS_N O AJ6 DRAM0_CS_N O AJ7 GND P AJ8 VDD26 P AJ9 VDD26 P AJ10 GND P AJ11 VDD26 P AJ12 GND P AJ13 GND P AJ14 GND P AJ15 GND P AJ16 GND P AJ17 GND P AJ18 GND ...

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... IDT 89TTM552 Pin Signal Type AL13 DRAM0_D16 B AL14 DRAM0_D17 B AL15 VDD26 P AL16 VDD26 P AL17 VDD26 P AL18 GND P AL19 GND P AL20 GND P AL21 VDD26 P AL22 VDD26 P AL23 VDD26 P AL24 VDD26 P AL25 DRAM1_D24 B AL26 DRAM1_DQS02 B AL27 DRAM1_D20 B AL28 GND P AL29 GND P AL30 DRAM1_DQS01 ...

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... IDT 89TTM552 Pin Signal Type AN25 DRAM1_D27 B AN26 DRAM1_D17 B AN27 DRAM1_D21 B AN28 DRAM1_D19 B AN29 DRAM1_D14 B AN30 DRAM1_D12 B AN31 DRAM1_D08 B AN32 DRAM1_D09 B AN33 DRAM1_D02 B AN34 VDD26 P AN35 DRAM1_D07 B AN36 DRAM1_D06 B AN37 DRAM1_ADDR00 O AP1 DRAM0_D01 B AP2 DRAM0_D37 B AP3 DRAM0_D39 B AP4 GND P AP5 GND ...

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... IDT 89TTM552 Pin Signal Type AR37 DRAM_CLKP00 O AT1 VDD26 P AT2 VDD26 P AT3 DRAM0_D69 B AT4 DRAM0_DQS08 B AT5 DRAM0_D66 B AT6 DRAM0_ADDR12 O AT7 DRAM0_ADDR09 O AT8 DRAM0_ADDR07 O AT9 DRAM0_ADDR03 O AT10 DRAM0_ADDR01 O AT11 DRAM0_D62 B AT12 DRAM0_DQS07 B AT13 DRAM0_D57 B AT14 DRAM0_D55 B AT15 DRAM0_D51 B AT16 DRAM0_D50 B AT17 DRAM0_D45 ...

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... IDT 89TTM552 89TTM552 Package 89TTM552 Package 89TTM552 Package 89TTM552 Package The package is an ASE HFCBGA-HP, having 1192 pins, with 1 mm pitch ×37 pin array; and a 40 × enclosure.Figure 7 shows the package geometry. Figure 7 89TTM552 Package Diagram April 7, 2005 ...

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... March 11, 2005: In Table 10, for signal PLL_CFG_OVR, “low” was changed to “high” in the Remarks column. Also in Table 10, the following signals were changed to read “pulldown”: PLL_RST, PLL_DIV_RST, PLL_CFG_OVR, PLL_RX_RST, PLL_TX_RST. April 7, 2005: On page 1, added information to clarify support of 89TTM552 Interfaces. CORPORATE HEADQUARTERS ...