89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 19

• Manufacturer Part Number: 89ttm552
• Description: Standalone 10g Simplex Traffic Manager
• Manufacturer: Integrated Device Technology

that meets the maximum ambient temperature requirements of their system.
thermal resistance of the package (junction to case + case to ambient) and is mainly specified as a reference parameter. (This is when a heat sink is
not present and the top surface of the package is essentially acting as the heat sink). However, in devices that have high power dissipation, heat sink
usage is highly desirable. Consequently, system designers may have limited use for this parameter.
8 8 8 8 9TTM552 Reset Sequence
section describes the reset sequence for the 89TTM552 device.
PLL_CFG_OVR pin controls this feature. When left high, the PLL will determine its clock frequency by sampling these values on the ZBus pins. The
feature is not necessary if the default clock frequencies are desired. (The default frequency for the core clock is 133 MHz and 500 MHz for transmit
and receive LVDS interfaces when a 100 MHz clock reference is used.) When default frequencies are desired, the PLL_CFG_OVR should be held low
and it is not necessary to drive the ZBus data and parity lines during the reset.
Core, LVDS Receive and Transmit PLL Frequency Setting
Core, LVDS Receive and Transmit PLL Frequency Setting
Core, LVDS Receive and Transmit PLL Frequency Setting
Core, LVDS Receive and Transmit PLL Frequency Setting
properly. Note that the setting is based on a 100MHz reference input clock (PLL_SYS_REFCLK pin).
IDT 89TTM552
9TTM552 Reset Sequence
9TTM552 Reset Sequence
9TTM552 Reset Sequence
The following graph depicts the ambient temperature (T
For system designers, specification of the maximum device junction temperature (operating) is critical, since it allows them to select a heat sink
The other parameter that is device package-specific is
A PLL reset sequence must be followed when resetting the 89TTM552 to ensure that clocks are stable when the chip comes out of reset. This
The 89TTM552 uses data presented on the ZBus data and parity pins to determine the clock frequencies when the chip is in reset. The
The reset sequence is summarized as follows:
1. Assert chip reset.
2.
3. Reset PLLs.
4. Release reset on PLLs.
5. Release chip reset.
6. Release LOR value on ZBus.
The following values must be driven on ZBUS_AD[ ] and ZBUS_PRTY before the reset sequences in order to set the chip operation frequency
ON forever).
Drive LOR (latch on reset) values on ZBus (described below) and enable configuration override on all PLLs. (Configuration override remains
80.0
70.0
60.0
50.0
40.0
30.0
1.0
72.2
Figure 5 89TTM552 Ambient Temperature Curve
2.0
66.4
Ø
A
) versus
JA
Ambient Temp. vs Ø
, without a heat sink, and is specified for various air-flow conditions. This is the intrinsic
3.0
62.0
Ø
19 of 37
CA.
Ø
4.0
CA
58.5
o
C/W
5.0
55.6
CA
6.0
53.2
7.0
51.2
8.0
49.5
April 7, 2005