89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 4
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89ttm552
Manufacturer Part Number
89ttm552
Description
Standalone 10g Simplex Traffic Manager
Manufacturer
Integrated Device Technology
Datasheet
1.89TTM552.pdf
(37 pages)
- Current page: 4 of 37
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8 8 8 8 9TTM55x
IDT 89TTM552
9TTM55x
9TTM55x
9TTM55x D D D D iagra
SIX-over-LVDS
Streaming
Interface
SPI-4.2
iagra
iagrams
iagra
or
or
(from PHY)
89TTM552
89TTM553
(to PHY)
ms
ms
ms
Thresholding
Thresholding
DSR,
BRX
Engine (AC)
Engine (AC)
Forwarding
Forwarding
Ingress
Egress
Rx
Engine (DFC)
Data Buffer Memory (DDR SDRAM)
and
and
Multicast
Figure 2 Example of a Full-duplex 10 Gbps System Configuration
Memory Controller
89TTM552-to-89TTM553
Figure 1 89TTM55x Functional Block Diagram
(PBC)
Framer
Extended Scheduler
NPU
NPU
Queue Manager
Queue Manager
or
Interface
Interface
(QM)
(QM)
Control Path SAR
LVDS
16-bit
(SAR)
Rx
Tx
4 of 37
89TTM552
89TTM552
89TTM553
(VOQM, BPQ)
OQ Manager
Ingress
Egress
(ARS, GS,
Scheduler
Packet
WFQ)
Scheduler
Packet
(SS)
Optional Flow-Based
Scheduler
LVDS
16-bit
Rx
Tx
Interface (CPIF, DMA)
Interface (CPIF, DMA)
CPU and Peripheral
CPU and Peripheral
SAR (ILS)
Datapath
AAL-5
(89TSF)
Switch
Fabric
Processor
Processor
Statistics
Statistics
(SP)
(SP)
DST,
BTX
Tx
SPI-4.2
or
Streaming
Interface
or
CSIX-over-LVD
External
Statistics
Port
ZBus
ZBus
April 7, 2005
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