MB86831 FUJITSU [Fujitsu Component Limited.], MB86831 Datasheet - Page 14

• Manufacturer Part Number: MB86831
• Description: 32-bit Embedded Controller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

14
MB86830 Series
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ERROR#
ASI<3:0>
LOCK#
RDYOUT#
IDLEEN
BMODE8#
BMODE16#
Symbol
ERROR SIGNAL
ADDRESS
SPACE
IDENTIFIERS
BUS LOCK
READY OUTPUT
IDLE ENABLE
BOOT MODE 8
BOOT MODE 16
Pin name
I/O
I/O
O
O
O
I
I
Error signal.
This pin outputs an error signal indicating that the CPU has stopped in
the error state resulting from a trap occurring with traps disabled. The
CPU can exit the error state only by a reset.
ASI pin (address space identification signal) or ADR pin.
Setting the ASISEL pin to “H” selects the ASI pin; setting it to “L” selects
the ADR<28:31> pin on the MB86832/834 or ADR<24:27> pin on the
MB86833/835/836. When the ASISEL pin is set to “L”, the “L” input to
the AS# pin is prohibited. A choice of these pins is supported by the
MB8682/833/834/835/836 but not by the MB86831-66/80 (only
ASI<3:0> is available).
Like the ADR<27:2> pin (ADR<23:2> pin on the MB86833/835/836),
this pin remains enabled for output during the bus cycle. The ASI pin
serves as an input in the bus grant state, used for CS generation and
internal resource address decoding. When ASI<3:0> is input from an
external device, ASI<7:4> is handled as “0” in the CPU.
Bus lock signal.
During execution of the Atomic Load Store instruction, the CPU asserts
the LOCK# signal to indicate that the current bus transaction requires
multiple transfers which cannot be divided. At a bus request (BREQ#)
during execution of an atomic instruction, the CPU releases the bus (by
asserting the BGRNT# signal) upon completion of the instruction exe-
cution. For normal use (where bus access permission is controlled by
BREQ#/BGRNT#), the LOCK# signal need not be used.
Ready signal output.
This pin outputs the composite signal consisting of the ready signal
generated by the internal wait state generator circuit and the external
ready signal (READY#). While the delay of the internally generated
ready signal is regulated based on the clock input, the input from the
pin is output delayed as it is at the timing of generation of the external
ready signal.
Idle insertion enable pin.
If the cycle that follows access to the CS0# area is load or store oper-
ation when this pin is at the “H” level, the CPU starts the next bus cycle
after inserting two idle clock cycles. This is efficient when EPROM
which takes long data bus output off time is connected directly to the
CPU.When this pin is at the “L” level, the CPU inserts only one idle cy-
cle before a write cycle immediately after a read cycle (this control is
compatible with conventional SPARClite processors).
Fix this pin at the “H” or “L” level.
CS0# area bus width setting signals.
These pins input signals at a reset to determine the bus width of the
CS0# area. Setting the BMODE8# pin to “L” selects the 8-bit bus
mode; setting the BMODE16# pin to “L” selects the 16-bit bus mode.
(The bus width for the CS1#-CS5# area is specified by the Bus Width/
Cacheable Control Register (BWCR).)
Fix these pins to “L” or “H”. However, it is not allowed to set both of
them to “L”.
Function
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