MB86831 FUJITSU [Fujitsu Component Limited.], MB86831 Datasheet - Page 56

• Manufacturer Part Number: MB86831
• Description: 32-bit Embedded Controller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

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MB86830 Series
3. Address Space
The MB86830 series has a wide addressable range in which user and supervisor spaces can be defined indepen-
dently. Of 30 lines of addresses, eight lines of address space identifiers (ASI) are used to distinguish between
protected and unprotected spaces. Tow of 256 different ASI values are used to define the user data and user in-
struction spaces; the rest are used to define the supervisor space.
When a reset, synchronous trap, or asynchronous trap occurs, the processor enters the supervisor mode. In the
supervisor mode, the processor executes instructions in the supervisor space and transfers data. The processor
can access other ASI values even when staying in the supervisor mode. The processor can use the remaining ASI
values, excluding the reserved values, to allocate other spaces as application definable spaces.
By distinguishing between the user and supervisor spaces, hardware can prevent inadvertent or unauthorized ac-
cess to system resources. When a real-time operating system (RTOS) is developed, for example, individual spac-
es provide the mechanism for separating the RTOS space efficiently from the user space.
4. Registers
The register set of the MB86830 series is made up of the registers to be used for general-purpose functions and
those to be used for control and status report purpose. The MB86830 series has 136 general-purpose registers
divided into eight global registers and a stack of eight register blocks (register windows). Each register window
incorporates 24 registers, of which eight registers are local to that window, eight “out” registers are overlapping the
next register window, and eight “in” registers are overlapping the previous register window. (See “General register
composition”.)
This register configuration allows a parameter to be passed to a subroutine. The next register window is made
• Integer operation unit internal block diagram
Instruction
(I block)
I data
m_ir
w_ir
block
e_ir
ir
I address
inc (+4)
Address block
(A block)
m_pc
d_pc
e_pc
0
adder
pc
TBR
Execution block
PSR/WIM/Y
read1
(E block)
A
ALU / Shifter
R
Data address
read2
D address
B
Register file
st_align
D data
read3
W
Id_align
write