MB86831 FUJITSU [Fujitsu Component Limited.], MB86831 Datasheet - Page 16

• Manufacturer Part Number: MB86831
• Description: 32-bit Embedded Controller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

16
MB86830 Series
(Continued)
O (V) :The circuit is active with the output at a valid level.
O (X) :The circuit is inactive with the output indeterminate.
O (Z) :Output pins and High-Z.
O (H) :The “H”level is output.
O (L) :The “L” level is output.
I (Z) :Input pins and High-Z
I (D) :When the DRAM controller has been enabled, the pin is switched to serve as an output, from the clock cycle
OVF#
SAMEPAGE#
FLOAT#
ADR<27:2>
AS#
BE0#
BE2#
CS0# to CS5#
ERROR#
LOCK#
PDOWN#
PBREQ#
SAMEPAGE#
• State of pins
Symbol
Pin symbol
that follows the clock cycle in which the AS# pin becomes “L”, and remains as the output until the ready
signal input pin becomes “L”. When the DRAM controller has been disabled, the pin enters the High-Z state.
TIMER OVER-
FLOW
SAME PAGE
DETECT
FLOATING
Pin name
At reset
O (X)
O (H)
O (X)
O (X)
O (H)
O (H)
O (H)
O (H)
O (H)
O (H)
I/O
O
O
At bus grant
I
O (H)
O (Z)
O (V)
O (V)
O (Z)
O (V)
O (V)
Timer overflow signal.
This pin outputs the “L” pulse when the timer reaches 0 after starting
counting according to the settings in the DRAM Refresh Timer Register
and DRAM Refresh Timer Pre-load Register with the TIMER ON/OFF
bit in the System Support Control Register (SSCR) set to “1” The pulse
width is the 1-clock width of the external bus clock when bit 31 in the
DRAM Refresh Timer Pre-load Register is “0”. When the bit is “1”, the
pulse width is the 3-clock width.
The timer performs counting based on the external bus clock.
Although this pin is used usually for the DRAM refresh request signal,
it can be connected to the interrupt input (IRQx) of the interrupt control-
ler (IRC) when the pulse width has been specified as the 3-clock width.
Same-page detection output pin.
When the Same-Page Enable bit in the System Support Control Reg-
ister (SSCR) has been “1”, this pin outputs the“L” level if the CS4# pin
is at the “L” level and if the address masked by the Same-Page Mask
Register (SPGMR) matches the previously accessed address when
compared.
The SAMEPAGE# signal remains output during the bus cycle.
Pin float input.
Fixing this pin at the “L” level puts all of the output pins and bidirectional
pins to the High-Z state.
I (D)
I (Z)
I (Z)
D<31:0>
RDWR#
BE1#
BE3#
BGRNT#
ASI<3:0>
RDYOUT#
BMREQ#
OVF#
Pin symbol
Function
At reset
O (H)
O (X)
O (X)
O (H)
O (X)
O (V)
O (H)
O (H)
I (Z)
At bus grant
O (Z)
O (Z)
O (V)
O (H)
O (V)
O (L)
I (Z)
I (Z)
I (Z)