MB86831 FUJITSU [Fujitsu Component Limited.], MB86831 Datasheet - Page 62

• Manufacturer Part Number: MB86831
• Description: 32-bit Embedded Controller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

62
MB86830 Series
(4)Y Register (Y)
(5)Ancillary State Register 17 (ASR17)
bit 31 to bit 1
bit 0
13. IU (Integer Unit) General-Purpose Registers (Not Memory Mapped)
The IU (integer unit) contains 136 32-bit general-purpose registers for holding arguments for operations and their
results. Of these registers, only 32 registers can be accessed through blocks called register windows.
The integer unit has eight register windows. The register window to be used is determined by the CWP bits (bits
2 to 0) in the Processor Status Register (PSR). Each register window consists of eight global registers available
commonly to all register windows and 24 registers (in-register
isters and out-registers are used commonly between adjacent register windows.
(1)Zero Register (r0)
bit 31 to bit 0
(2)General register (r1 to r31)
14. Bit map of register with built-in CPU core
(1)Cache/BIU Control Register (CBIR)
bit 31 to bit 10 :Reserved [“0”Write, Don’t care for read]
bit 9 to bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Don’t care at reset.
bit
bit
bit
bit
bit
31
31
31
31
31
:Reserved [“0”Write, Don’t care for read]
:Single Vector Trapping [SVT] (Enable
:Non-cacheable Wait-state [Don’t care for read]
:Cacheability Enable [Don’t care for read] (Enable
:Reserved [“0”Write, Don’t care for read]
:Write Buffer Enable (Enable
:Prefetch Buffer Enable (Enable
:Data Cache Lock (Lock
:Data Cache Enable (Enable
:Instruction Cache Lock (Lock
:Instruction Cache Enable (Enable
:0
Reserved
1, Unlock
1, Disable
1, Disable
1, Unlock
1, Disable
1, Disable
Reserved
0, RST
1, Disable
0, RST
0, RST
0, RST
0
0, RST
8, local register
0)
0, RST
1, Disable
0)
0)
0, RST
10
0)
0)
9
0)
ASI= 0x01, Address= 0x00000000
0)
8
0, RST
8, out-register
7
6
0)
5
4
8). The in-reg-
3
2
1
1
SVT
0
0
0
0
0
H