ISL12022 INTERSIL [Intersil Corporation], ISL12022 Datasheet - Page 18

• Manufacturer Part Number: ISL12022
• Manufacturer: INTERSIL [Intersil Corporation]

For the 10 minute temperature period the average current is
shown in Equation 2:
If the application has a stable temperature environment that
doesn’t change quickly, the 10 minute option will work well
and the backup battery lifetime impact is minimized. If quick
temperature variations are expected (multiple cycles of more
than 10° within an hour), then the 1 minute option should be
considered and the slightly higher battery current figured into
overall battery life.
GAIN FACTOR OF AT BIT (BETA<4:0>)
Beta is specified to take care of the Cm variations of the
crystal. Most crystals specify Cm around 2.2fF. For example,
if Cm > 2.2fF, the actual AT steps may reduce from
1ppm/step to approximately 0.80ppm/step. Beta is then used
to adjust for this variation and restore the step size to
1ppm/step.
BETA values are limited in the range from 01000 to 11111 as
shown in Table 16
two AT settings as shown in Equation 3:
where:
AT(max) = F
AT(min) = F
The BETA VALUES result is indexed in the right hand
column and the resulting Beta factor (for the register) is in
the same row in the left column.
The value for BETA should only be changed while the TSE
(Temperature Sense Enable) bit is “0”. The procedure for
writing the BETA register involves two steps. First, write the
new value of BETA with TSE = 0. Then write the same value
of BETA with TSE = 1. This will insure the next temperature
sense cycle will use the new BETA value.
ΔI
BETAVALUES
BAT
=
0.022s
----------------- -
600s
BETA<4:0>
OUT
OUT
01000
00110
00101
00100
00011
00010
00001
00000
10000
10001
00111
×
=
68μA
in ppm (at AT = 3FH).
in ppm (at AT = 00H) and
TABLE 16. BETA VALUES
(
.
AT max
To use Table 16, the device is tested at
(
=
25nA
) AT min
–
18
(
AT STEP ADJUSTMENT
)
)/63
0.5000
0.5625
0.6250
0.6875
0.7500
0.8125
0.8750
0.9375
1.0000
1.0625
1.1250
(EQ. 2)
(EQ. 3)
ISL12022
Final Analog Trimming Register (FATR)
This register shows the final setting of AT after temperature
correction. It is read-only; the user cannot overwrite a value to
this register. This value is accessible as a means of monitoring
the temperature compensation function. See Table 17.
Final Digital Trimming Register (FDTR)
This Register shows the final setting of DT after temperature
correction. It is read-only; the user cannot overwrite a value
to this register. The value is accessible as a means of
monitoring the temperature compensation function. The
corresponding clock adjustment values are shown in
Table 19. The DT setting has both positive and negative
settings to adjust for any offset in the crystal.
.
ADDR
ADDR
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL
0Eh
0Fh
FDTR<2:0>
TABLE 17. FINAL ANALOG TRIMMING REGISTER
TABLE 18. FINAL DIGITAL TRIMMING REGISTER
00000
00001
00010
7
0
7
0
BETA<4:0>
TABLE 16. BETA VALUES (Continued)
DIGITAL TRIMMING REGISTER
10010
10100
10101
10011
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
6
0
6
0
FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
5
0
5
FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
4
DECIMAL
4
0
1
2
3
AT STEP ADJUSTMENT
3
2
1.1875
1.2500
1.3125
1.3750
1.4375
1.5000
1.5625
1.6250
1.6875
1.7500
1.8125
1.8750
1.9375
2.0000
2
ADJUSTMENT
ppm
30.5
61
1
0
June 23, 2009
1
FN6659.2
0
0