ISL12022 INTERSIL [Intersil Corporation], ISL12022 Datasheet - Page 24

• Manufacturer Part Number: ISL12022
• Manufacturer: INTERSIL [Intersil Corporation]

The ISL12022 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again, after successful receipt of an Address Byte. The
ISL12022 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifiers. These
bits are “1101111” for the RTC registers and “1010111” for the
User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 17).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12022 compares the device identifier and device select
bits with “1101111” or “1010111”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power-up, the internal address
counter is set to address 00h, so a current address read starts
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Bytes, as shown in
Figure 20.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
FIGURE 17. SLAVE ADDRESS, WORD ADDRESS, AND DATA
A7
D7
1
A6
D6
1
A5
D5
0
BYTES
A4
D4
1
A3
D3
SIGNALS FROM
SIGNAL AT SDA
1
SIGNALS FROM
THE MASTER
THE ISL12022
FIGURE 16. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
24
1
A2
D2
1
A1
D1
R/W
A0
D0
S
T
A
R
T
SLAVE
ADDRESS BYTE
WORD ADDRESS
DATA BYTE
1
IDENTIFICATION
1
0
BYTE
1
1 1 1
ISL12022
0
WRITE
A
C
K
0 0 0 0
ADDRESS
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12022 responds with an ACK. At this time, the I
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction, followed
by one or more Data Bytes (see Figure 20). The master initiates
the operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W
bit set to “1”. After each of the three bytes, the ISL12022
responds with an ACK. Then the ISL12022 transmits Data
Bytes as long as the master responds with an ACK during the
SCL cycle following the eighth bit of each byte. The master
terminates the read operation (issuing a STOP condition)
following the last bit of the last Data Byte (see Figure 20).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer’s initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 2Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
BYTE
TABLE 26. SUGGESTED SURFACE MOUNT CRYSTALS
MANUFACTURER
SaRonix
Ecliptek
Raltron
Citizen
Epson
ECS
Fox
A
C
K
DATA
BYTE
A
C
K
ECPSM29T-32.768K
MC-405, MC-406
S
T
O
P
PART NUMBER
RSM-200S
ECX-306
FSM-327
CM200S
32S12
June 23, 2009
2
C
FN6659.2