74VHC08M Fairchild Semiconductor, 74VHC08M Datasheet

IC GATE AND QUAD 2 INPUT 14-SOIC

74VHC08M

Manufacturer Part Number
74VHC08M
Description
IC GATE AND QUAD 2 INPUT 14-SOIC
Manufacturer
Fairchild Semiconductor
Series
74VHCr
Datasheets

Specifications of 74VHC08M

Logic Type
AND Gate
Number Of Inputs
2
Number Of Circuits
4
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Product
AND
Logic Family
74VHC
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Propagation Delay Time
12.3 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Output Current
8mA
No. Of Inputs
8
Supply Voltage Range
2V To 5.5V
Logic Case Style
SOIC
No. Of Pins
14
Operating Temperature Range
-40°C To +85°C
Filter Terminals
SMD
Rohs Compliant
Yes
Family Type
VHC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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©1992 Fairchild Semiconductor Corporation
74VHC08 Rev. 1.4.0
74VHC08
Quad 2-Input AND Gate
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74VHC08M
74VHC08SJ
74VHC08MTC
High Speed: t
High noise immunity: V
Power down protection is provided on all inputs
Low power dissipation: I
Low noise: V
Pin and function compatible with 74HC08
Order Number
All packages are lead free per JEDEC: J-STD-020B standard.
OLP
PD
4.3ns (Typ.) at T
0.8V (Max.)
NIH
CC
Package
Number
MTC14
M14D
M14A
V
2µA (Max.) @ T
NIL
A
28% V
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
25°C
CC
A
(Min.)
25°C
General Description
The VHC08 is an advanced high speed CMOS 2 Input
AND Gate fabricated with silicon gate CMOS technol-
ogy. It achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
The internal circuit is composed of 4 stages including
buffer output, which provide high noise immunity and
stable output. An input protection circuit insures that 0V
to 7V can be applied to the input pins without regard to
the supply voltage. This device can be used to interface
5V to 3V systems and two supply systems such as bat-
tery backup. This circuit prevents device destruction due
to mismatched supply and input voltages.
Package Description
December 2007
www.fairchildsemi.com

Related parts for 74VHC08M

74VHC08M Summary of contents

Page 1

... Order Number Number 74VHC08M M14A 74VHC08SJ M14D 74VHC08MTC MTC14 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1992 Fairchild Semiconductor Corporation 74VHC08 Rev. 1.4.0 General Description 25° ...

Page 2

... Connection Diagram Pin Description Pin Names Inputs Outputs n ©1992 Fairchild Semiconductor Corporation 74VHC08 Rev. 1.4.0 Logic Symbol Truth Table Description IEEE/IEC www.fairchildsemi.com ...

Page 3

... OPR Input Rise and Fall Time 3.3V ± 0. 5.0V ± 0.5V CC Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1992 Fairchild Semiconductor Corporation 74VHC08 Rev. 1.4.0 Parameter (1) Parameter 3 Rating –0.5V to +7.0V –0.5V to +7.0V –0. 0.5V CC –20mA ±20mA ±25mA ± ...

Page 4

... OL (2) V Quiet Output Minimum OLV Dynamic V OL (2) V Minimum HIGH Level IHD Dynamic Input Voltage 2) V Maximum LOW Level ILD Dynamic Input Voltage Note: 2. Parameter guaranteed by design. ©1992 Fairchild Semiconductor Corporation 74VHC08 Rev. 1.4.0 (V) Conditions Min. 1.50 0 –50µA 1 2.9 4.4 I – ...

Page 5

... PD current consumption without load. Average operating current can be obtained by the equation: I (opr.) C • V • ©1992 Fairchild Semiconductor Corporation 74VHC08 Rev. 1.4.0 V (V) Conditions Min. CC 3.3 ± 0.3 C 15pF L C 50pF L 5.0 ± ...

Page 6

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 9

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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