lc75884e Sanyo Semiconductor Corporation, lc75884e Datasheet
lc75884e
Related parts for lc75884e
lc75884e Summary of contents
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... Ordering number : EN6086 1/4 Duty LCD Display Drivers with Key Input Function Overview The LC75884E and LC75884W are 1/4 duty LCD display drivers that can directly drive up to 220 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from keys to reduce printed circuit board wiring ...
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... CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time DO output delay time DO rise time Note: *1. Since open-drain output, these values depend on the resistance of the pull-up resistor R LC75884E, LC75884W =0V SS Symbol Conditions V max V DD ...
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... Output off leakage current Output high level voltage Output low level voltage Output middle level voltage *2 Oscillator frequency Current drain Nete: *2. Excluding the bias voltage generation divider resistor built into V LC75884E, LC75884W Symbol Conditions V CE, CL, DI, RES, KI1 to KI5 H V DET ...
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... When CL is stopped at the low level 2. When CL is stopped at the high level LC75884E, LC75884W Figure 1 Figure 2 No. 6086-4/27 ...
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... Pin Assignment LC75884E, LC75884W No. 6086-5/27 ...
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... Block Diagram LC75884E, LC75884W No. 6086-6/27 ...
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... LCD driver block power supply connection. Provide a voltage LCD between VDD–0.5 and 6.0V Power supply connection. Connect to ground. SS LC75884E, LC75884W Function /512)Hz. OSC Key scan disabled All key data is reset to low Key scan enabled Handling Active I/O when unused — ...
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... Serial Data Input 1. When CL is stopped at the low level Note B3, ........ CCB address DD ................................ Direction data LC75884E, LC75884W No. 6086-8/27 ...
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... Note B3, ........ CCB address DD ................................ Direction data CCB address ........ 42H D1 to D220 ............ Display data S0,S1 .................... Sleep control data K0,K1 .................... Key scan output/segment output selection data ................ Segment output port/general-purpose output port selection data SC ........................ Segment on/off control data DR ........................ 1/2 bias or 1/3 bias drive selection data LC75884E, LC75884W No. 6086-9/27 ...
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... D5 S3/P3 D9 S4/P4 D13 For example, if the S4/P4 output pin is selected general-purpose output port, the S4/P4 output pin will output a high level (V D13 is 1, and will output a low level (Vss) when D13 is 0. LC75884E, LC75884W Segment outputs OSC oscillator Common outputs Operating Operating Stopped ...
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... D101 D102 D103 S27 D105 D106 D107 S28 D109 D110 D111 Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S54 and KS2/S55 are selected for use as segment outputs. LC75884E, LC75884W COM4 Output pin COM1 D4 S29 D113 D8 S30 D117 D12 S31 ...
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... SA ........................ Sleep acknowledge data Note key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid. LC75884E, LC75884W The LCD segments for COM1,COM2,COM3 and COM4 are off. The LCD segment for COM4 is on. ...
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... This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the control data bits, even in sleep mode. (See the control data description for details.) LC75884E, LC75884W KI3 KI4 ...
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... CE is high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75884E/W performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ ...
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... CE is high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75884E/W performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ ...
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... LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on. LC75884E, LC75884W 1/4 Duty, 1/2 Bias Waveforms VLCD VLCD1, VLCD2 0 V VLCD ...
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... LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on. LC75884E, LC75884W 1/4 Duty, 1/3 Bias Waveforms VLCD VLCD1 VLCD2 0 V ...
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... System Reset The LC75884E/W supports the reset methods described below. When a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning become possible. ...
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... Reset when the logic block power supply voltage is in the allowable operating range (V The system is reset when the RES pin is set low, and the reset is cleared by setting RES pin high. 2. LC75884E/W internal block states during the reset period • CLOCK GENERATOR Reset is applied and the base clock is stopped ...
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... S0 and S1 control data bits have been transferred. *7.Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period even if a key data read operation is performed. LC75884E, LC75884W No. 6086-20/27 ...
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... The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. LC75884E, LC75884W fall time when power drops are both at least 1 ms, as the LC75884E/W is reset by the VDET. DD rise time when power is applied and the DD ...
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... The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. LC75884E, LC75884W fall time when power drops are both at least 1 ms, as the LC75884E/W is reset by the VDET. DD rise time when power is applied and the DD ...
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... The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. LC75884E, LC75884W fall time when power drops are both at least 1 ms, as the LC75884E/W is reset by the VDET. DD rise time when power is applied and the DD ...
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... Notes on transferring display data from the controller The display data (D1 to 220) is transferred to the LC75884E/W in four operations. All of the display data should be transferred within maintain the quality of the displayed image. LC75884E, LC75884W fall time when power drops are both at least 1 ms, as the LC75884E/W is reset by the VDET ...
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... The period t9 in this technique must satisfy the following condition. t9>t6+t7+ key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. LC75884E, LC75884W ——— fosc No. 6086-25/27 ...
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... Key scan execution time when the key data agreed for two key scans. (800T(S)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600T(S)) t7: Key address (43H) transfer time t8: Key data read time LC75884E, LC75884W ——— fosc No. 6086-26/27 ...
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... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1999. Specifications and information herein are subject to change without notice. LC75884E, LC75884W PS No. 6086-27/27 ...