lc75884e Sanyo Semiconductor Corporation, lc75884e Datasheet - Page 19

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lc75884e

Manufacturer Part Number
lc75884e
Description
1/4 Duty Lcd Display Drivers With Key Input Function
Manufacturer
Sanyo Semiconductor Corporation
Datasheet
(2) Reset when the logic block power supply voltage is in the allowable operating range (V
2. LC75884E/W internal block states during the reset period
The system is reset when the RES pin is set low, and the reset is cleared by setting RES pin high.
• CLOCK GENERATOR
• COMMON DRIVER, SEGMENT DRIVER & LATCH
• KEY SCAN
• KEY BUFFER
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
Reset is applied and all the key data is set to low.
Since serial data transfer is possible, these circuits are not reset.
LC75884E, LC75884W
Note: t1 ≥ 1 [ms] (Logic block power supply voltage V
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage V
DD
= 4.5 to 6.0V)
No. 6086-19/27
DD
DD
rise time)
fall time)

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