bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 18

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

8
1.0 Functional Description
1.2 Pin Descriptions
Table 1-2. Pin Descriptions Grouped By Pin Function (1 of 4)
45, 50, 55,
57
53
52
67
59
41
43
49
62
19
18
14
15
64
73
74
51
46
63, 68
70
69
Pin #
I/O
I/O
O
O
A
A
A
A
A
A
A
A
A
A
A
I
I
I
I
I
I
I
Pin Name
MUX[3:0]
SYNCDET
MUXOUT
AGCCAP
REFOUT
CLEVEL
YREF+
YREF–
CREF+
CREF–
I2CCS
SDA
RST
SCL
YIN
CIN
N/C
N/C
N/C
N/C
N/C
Analog composite video inputs to the on-chip input multiplexer. They are used to
select between four composite sources or three composite and one S-Video source.
Unused pins should be connected to GND.
The analog video output of the 4-to-1 multiplexer. Connected to the YIN pin.
The analog composite or luma input to the Y-ADC.
The analog chroma input to the C-ADC.
The sync stripper input generates timing information for the AGC circuit. Can be
optionally connected through a 0.1 F capacitor to the same source as the Y-ADC, to
maintain compatibility with Bt829 board layouts. A 1 M bleeder resistor can be
connected to ground, to maintain compatibility with Bt829 board layouts. For new
Bt829B designs, this pin may be connected to VAA.
The AGC time constant control capacitor node. Must be connected to a 0.1 F capac-
itor to ground.
Output of the AGC which drives the YREF+ and CREF+ pins.
The top of the reference ladder of the Y-ADC. This should be connected to REFOUT.
The bottom of the reference ladder of the Y-ADC. This should be connected to analog
ground (AGND).
The top of the reference ladder of the C-ADC. This should be connected to REFOUT.
The bottom of the reference ladder of the C-ADC. This should be connected to analog
ground (AGND).
An input to provide the DC level reference for the C-ADC. For compatibility with
Bt829 board layouts, the 30 k divider resistors may be maintained.
Note: This pin should be left to float for new Bt829B designs.
No connect.
No connect.
No connect.
No connect.
No connect.
The I
The I
The I
devices in the same system. This pin is internally pulled to ground with an effective
18 K resistance.
Reset Control Input (TTL compatible). A logical 0 for a minimum of four consecutive
clock cycles resets the device to its default state. A logical 0 for less than eight XTAL
cycles will leave the device in an undetermined state.
2
2
2
C Serial Clock Line.
C Serial Data Line.
C Chip Select Input (TTL compatible). This pin selects one of two Bt829B
I
2
Input Stage Pins
C Interface Pins
D829BDSA
Description
VideoStream II Decoders
Bt829B/827B