bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 94

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

84
4.0 Control Register Definitions
0x04—Vertical Delay Register, Lower Byte (VDELAY_LO)
0x04—Vertical Delay Register, Lower Byte (VDELAY_LO)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0x16. The LSB
(LSB) is VDELAY_LO(0). This 8-bit register is the lower byte of the 10-bit VDELAY register. The CROP reg-
ister contains the two MSBs of VDELAY. VDELAY defines the number of half lines between the trailing edge
of VRESET and the start of active video.
VDELAY_LO
0x05—Vertical Active Register, Lower Byte (VACTIVE_LO)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0xE0. The LSB is
VACTIVE_LO(0). This 8-bit register is the lower byte of the 10-bit VACTIVE register. The CROP register con-
tains the two MSBs of VACTIVE. VACTIVE defines the number of lines used in the vertical scaling process.
The actual number of lines output by the Bt829A is SCALING_RATIO * VACTIVE.
VACTIVE_LO
0x06—Horizontal Delay Register, Lower Byte (HDELAY_LO)
The MPU can read or write to this control register at any time. Upon reset, it is initialized to 0x78.
HDELAY_LO(0) is the LSB. This 8-bit register is the lower byte of the 10-bit HDELAY register. The two
MSBs of HDELAY are contained in the CROP register. HDELAY defines the number of scaled pixels between
the falling edge of HRESET and the start of active video.
HDELAY_LO
7
0
7
1
7
0
0x01–0xFF = The LSByte of the vertical delay register.
0x00–0xFF = The LSByte of the vertical active register.
0x01–0xFF = the LSByte of the horizontal delay register. HACTIVE pixels are output by the
chip starting at the fall of HRESET.
6
0
6
1
6
1
Caution: HDELAY must be programmed with an even number.
5
0
5
1
5
1
4
1
4
0
4
1
D829BDSA
VACTIVE_LO
HDELAY_LO
VDELAY_LO
3
0
3
0
3
1
2
1
2
0
2
0
VideoStream II Decoders
1
1
1
0
1
0
Bt829B
0
0
0
0
0
0