bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 49

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

Bt829B/827B
VideoStream II Decoders
(i.e., 16-bit SPI, 8-bit SPI, and ByteStream modes). The range of the VBI data can
be controlled with the RANGE bit in the OFORM Register (0x12). It is necessary
to limit the range of VBI data for ByteStream output mode.
the status of the VPRES bit in the STATUS register in order for the Bt829B to
generate VBI data. If the status of the VPRES bit reflects no analog input, then the
Bt829B generates YCrCb data to create a flat blue field image.
ble. Setting the VBIFMT bit in the VTC register to a logical 0 places the nth data
sample on VD[15:8] and the nth+1 sample on VD[7:0]. Setting VBIFMT to a log-
ical 1, logical 0 reverses the above. Similarly, in ByteStream and 8-bit output
modes, setting VBIFMT = 0 generates a VBI sample stream with an ordering
sequence of n+1, n, n+3, n+2, n+5, n+4, etc. Setting VBIFMT = 1 for
ByteStream/8-bit output generates an n, n+1, n+2, n+3, etc. sequence as shown in
Figure 1-22.
Figure 1-22. VBI Sample Ordering
data output by the Bt829B:
The Bt829B can provide VBI data in all the pixel port output configurations
There must be a video signal present on the Bt829B analog input as defined by
The order in which the VBI data is presented on the output pins is programma-
A video processor/controller must be able to do the following to capture VBI
• Keep track of the line count in order to select a limited number of specific
• Handle data type transitioning on the fly from the vertical interval to the
• Handle a large and varying number of horizontal pixels per line in the VBI
VD[15:8]
VD[15:8]
lines for processing of VBI data.
active video image region. For example, during the vertical interval with
VBI data pass through enabled, it must grab every byte pair while HAC-
TIVE is high using the 4*Fsc clock or QCLK. However, when the data
stream transitions into YCrCb 4:2:2 data mode with VACTIVE going high,
the video processor must interpret the DVALID signal (or use QCLK for
the data load clock) from the Bt829B for pixel qualification and use only
valid pixel cycles to load image data (default Bt829B operation).
region as compared to the active image region.
VD[7:0]
CLKx1
CLKx2
D829BDSA
16-bit SPI Mode (VBIFMT = 0)
8-bit SPI Mode (VBIFMT = 1)
n+1
n
n
n+2
n+3
n+1
1.9 Bt829B VBI Data Output Interface
n+2
1.0 Functional Description
n+3
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