bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 40

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

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1.0 Functional Description
1.7 Video Scaling, Cropping, and Temporal Decimation
1.7.7 Cropping Registers
Horizontal Delay Register (HDELAY)
between the falling edge of HRESET and the rising edge of ACTIVE. The count
is programmed with respect to the scaled frequency clock.
NOTE:
Horizontal Active Register (HACTIVE)
number of active pixels per line of video. This is equivalent to the number of
scaled pixels that the Bt829B should output on a line. For example, if this register
contained 90, and HSCALE was programmed to down-scale by 4:1, then 90
active pixels would be output. The 90 pixels would be a 4:1 scaled image of the
360 pixels (at CLKx1) starting at count HDELAY. HACTIVE is restricted in the
following manner:
including blanking, sync and active regions. Therefore:
fore:
between HRESET and the first active pixel. Because the front porch is defined as
the distance between the last active pixel and the next horizontal sync, the video
line can be considered in three components: HDELAY, HACTIVE, and the front
porch. Figure 1-15 illustrates the video signal regions.
Figure 1-15. Regions of the Video Signal
For example, in the NTSC square pixel format, there is a total of 780 pixels,
When scaled by 2:1 for CIF, the total number of active pixels is 390. There-
The HDELAY register is programmed with the number of scaled pixels
HDELAY should always be an even number.
HDELAY
HACTIVE + HDELAY Total Number of Scaled Pixels.
D829BDSA
Porch
Front
HACTIVE + HDELAY 780.
HACTIVE +HDELAY 390.
HDELAY is programmed with the delay
HACTIVE is programmed with the actual
HACTIVE
VideoStream II Decoders
Bt829B/827B