em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 82

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em78p510nso32j/s

Manufacturer Part Number
em78p510nso32j/s
Description
8-bit Microprocessor With Otp Rom
Manufacturer
ELAN Microelectronics Corp
Datasheet
EM78P510N
8-Bit Microprocessor with OTP ROM
76 •
Below are the functions of each block and explanations on how to carry out the SPI
communication with the signals depicted in Figure 6-22 and Figure 6-23.
6.12.3 SPI Signal & Pin Description
PA4/SEG4/SI:
The detailed functions of the four pins, SI, SO, SCK, and /SS are as follows:
PA4/SEG4/SI: Serial Data In
PA5/SEG5/SO: Serial Data Out
PA6/SEG6/SCK:Serial Clock
PA7/SEG7//SS: /Slave Select (Option). This pin (/SS) may be required during a
RBF: Set by Buffer Full Detector
Buffer Full Detector: Set to 1 when an 8-bit shifting is completed.
SSE: Loads the data in SPIS register, and begin to shift
SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIR and the
SPIR reg.:Read buffer. The buffer will be updated as the 8-bit shifting is completed.
SPIW reg.: Write buffer. The buffer will deny any attempts to write until the 8-bit
The SSE bit will be kept in “1“ if the communication is still undergoing. This flag
SBRS2~SBRS0: Programming the clock frequency/rates and sources.
Clock Select: Selecting either the internal or the external clock as the shifting clock.
Edge Select: Selecting the appropriate clock edges by programming the CES bit
Serial Data In
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
Defined as high-impedance, if not selected
slave mode
SPIW registers are shift at the same time. Once data are written, SPIS starts
transmission / reception. The data received will be moved to the SPIR register as
the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the
SPIIF (SPI Interrupt) flag are then set.
The data must be read before the next reception is completed. The RBF flag is
cleared as the SPIR register reads.
shifting is completed.
must be cleared as the shifting is completed. Users can determine if the next write
attempt is available.
last
(This specification is subject to change without further notice)
Product Specification (V1.1) 01.25.2008

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