lxt384 Intel Corporation, lxt384 Datasheet - Page 85

• Manufacturer Part Number: lxt384
• Description: Octal T1/e1/j1 Short Haul Transceiver
• Manufacturer: Intel Corporation

9.3
Document Number: 248994
Revision Number: 004
Revision Date: September 22, 2005
Table 50. TAP State Description
TAP Controller
The TAP controller is a 16-state synchronous state machine controlled by the TMS input and
clocked by TCK (see
mode, receiving an instruction, receiving data, transmitting data or in an idle state.
describes in detail each of the states represented in
Test Logic Reset
Run -Test / Idle
Capture - DR
Shift - DR
Update - DR
Capture - IR
Shift - IR
Update - IR
Pause - IR
Pause - DR
Exit1 - IR
Exit1 - DR
Exit2 - IR
Exit2 - DR
State
In this state the test logic is disabled. The device is set to normal operation mode. While in
this state, the instruction register is set to the ICODE instruction.
The TAP controller stays in this state as long as TMS is Low. Used to perform tests.
The Boundary Scan Data Register (BSR) is loaded with input pin data.
Shifts the selected test data registers by one stage toward its serial output.
Data is latched into the parallel output of the BSR when selected.
Used to load the instruction register with a fixed instruction.
Shifts the instruction register by one stage.
Loads a new instruction into the instruction register.
Momentarily pauses shifting of data through the data/instruction registers.
Temporary states that can be used to terminate the scanning process.
Figure
16).The TAP controls whether the LXT384 Transceiver is in reset
Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Figure
Description
16.
Table 50
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