at7601fg AME, Inc., at7601fg Datasheet - Page 10

• Manufacturer Part Number: at7601fg
• Description: Printer Port Controller
• Manufacturer: AME, Inc.

10
AT7601F
5-3 Extended Capabilities Parallel (ECP) Port
5-2-5 EPP 1.9 Operation
5-2-6 EPP Version 1.7 Operation
ECP provides a number of advantages, some of which are listed below. The individual features are explained
in greater detail in the remainder of this section.
l
l
l
l
l
l
l
l
also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the
standard or bi-directional mode, and all output signals (STB, AFDD, INIT) are as set by the SPP Control
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in
the standard or bi-directional mode, and all output signals (STB, AFD, INIT) are as set by the SPP
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are
Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed
from the start of the EPP cycle (IOR# or IOW# asserted ) to WAIT# being deasserted (after command). If
a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit
always be in a write mode and the WRITE# signal to always be asserted.
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes
Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from
the start of the EPP cycle (IOR# or IOW# asserted) to the end of the cycle IOR# or IOW# deasserted). If
a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit
0.
High performance half-duplex forward and reverse channel
Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput(64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
0.
AME, Inc.
Printer Port Cotroller
Rev. B.02