at7601fg AME, Inc., at7601fg Datasheet - Page 22

• Manufacturer Part Number: at7601fg
• Description: Printer Port Controller
• Manufacturer: AME, Inc.

22
AT7601F
5-3-2.9 DMA Transfers
5-3-2.10 DMA Mode - Transfers from the FIFO to Host
5-3-2.11 Programmed I/O (NON-DMA) Mode
Restarting the DMA is accomplished by enabling DMA in the host, setting DMAEn to 1, followed by
DMA transfers are always to or from the ECP-DFIFO, T-FIFO or C-FIFO. DMA utilizes the standard PC
DMA services. To use the DMA transfers, the host first sets up the direction and state as in the pro-
grammed I/O case. Then it programs the DMA controller in the host with the desired count and memory
address. Lastly it sets DMAEn to 1 and Servicelntr to 0. The ECP requests DMA transfers from the host
by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate direction and
mode. When the terminal count in the DMA controller is reached, an interrupt is generated and
Servicelntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests dReq
shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting
be asserted for more than 32 DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted
until PDACK# is deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting
Servicelntr to 1, followed by setting DMAEn to 0, and waiting for the FIFO to become empty or full.
PDACK# and addresses need not be valid. PINTR is generated when a TC is received. RDRQ must not
transfers is with a TC.)
setting Servicelntr to 0.
Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software
can determine the WriteIntrThreshold, ReadlntrThreshold, and FIFO depth by accessing the FIFO in Test
Mode.
Programmed I/O transfers are to the ECP-DFIFO at 400H and ECP-AFIFO at 000H or from
The ECP-DFIFO located at 400H, or to/from the T-FIFO at 400H. To use the programmed I/O transfers,
the host first sets up the direction and state, sets DMAEn to 0 and Servicelntr to 0. The ECP requests
programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or
fill the FIFO using the appropriate direction and mode.
The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond
Servicelntr has been re-enabled. (Note: A data underrun may occur if PDRQ is not removed in time to
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to
transfer, even if the chip continues to request more data from the peripheral.)
to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO
becomes empty or when the TC becomes true (qualified by PDACK#), indicating that no more data is
required. PDRQ goes inactive after PDACK# goes active for the last byte of a data transfer (or on the
active edge of lOR#, on the last byte, if no edge is present on PDACK#). If PDRQ goes inactive due to
the FIFO going empty, then PDRQ is active again as soon as there is one byte in the FIFO. If PDRQ
goes inactive due to the TC, then PDRQ is active again when there is one byte in the FIFO, and
prevent an unwanted cycle.)
AME, Inc.
Printer Port Cotroller
Rev. B.02