at7601fg AME, Inc., at7601fg Datasheet - Page 13

• Manufacturer Part Number: at7601fg
• Description: Printer Port Controller
• Manufacturer: AME, Inc.

Rev. B.02
AT7601F
* Registers are in all modes.
** All FIFOs use one common 16-byte FIFO.
5-3-1.1 Data and ECP- AFIFO Port
Data
ECP-AFIFO
DSR
DCR
C-FIFO
ECP-DFIFO
T-FIFO
Cnfg-A
Cnfg-B
ECR
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The
Timing Diagram, located in the Timing Diagrams section of this data sheet.
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of '00H'from the base address. The data register is cleared at
bus on the rising edge of the IOW# input. The contents of this register are buffered (non inverting) and
output onto the PD0-PD7 ports. During a READ operation, PD0-PD7 ports are read and output to the
host CPU.
Mode 011 (ECP FIFO-Address/RLE)
hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this
register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward
AME, Inc.
Compress
Addr/RLE
BUSY#
PD7
D7
1
0
IntrValue
MODE
ACK#
PD6
D6
1
0
Table 10. Parallel Port and ECP Registers
PError
PDIR
PD5
IRQ
D5
0
ADDRESS OFFSET = 400H
Parallel Port Data FIFO
ErrIntrEn#
AckIntEn
SLCT
PD4
ECP Data FIFO
IRQ
D4
1
Test FIFO
Address or RLE field
En/Dis
Fault#
DMA
SLIN
PD3
IRQ
D3
0
Service
INIT#
DMA
PD2
Intr
Printer Port Controller
D2
1
0
FIFO
DMA
AFD
PD1
Full
D1
1
0
EMPTY
DMA
FIFO
PD0
STB
D0
1
0
NOTE
**
**
**
**
*
*
13