x25170 IC MICROSYSTEMS, x25170 Datasheet - Page 5

• Manufacturer Part Number: x25170
• Description: Spi Serial E 2 Prom With Block Lock ? Protection
• Manufacturer: IC MICROSYSTEMS

X25170
Figure 1. Read E
Figure 2. Read Status Register Operation Sequence
Write Sequence
Prior to any attempt to write data into the X25170, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25170. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
SCK
SO
CS
SI
2
High Impedance
PROM Array Operation Sequence
SCK
SO
CS
SI
0
1
Instruction
High Impedance
2
0
3
1
4
Instruction
5
2
6
3
7
4
15 14 13
8
5
9
6
16 Bit Address
10
7
To write data to the E
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to 32 bytes of data to the
X25170. The only restriction is the 32 bytes must reside
on the same page. If the address counter reaches the
end of the page and the clock continues, the counter will
“roll over” to the first address of the page and overwrite
any data that may have been written.
MSB
8
7
20 21 22 23 24 25 26 27 28 29 30
3
9
6
2
10 11 12 13 14
5
1
Data Out
4
0
3
MSB
Characteristics subject to change without notice.
7
2
6
2
PROM memory array, the user
1
5
0
Data Out
4
3
2
1
0
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