x25170 IC MICROSYSTEMS, x25170 Datasheet - Page 6

• Manufacturer Part Number: x25170
• Description: Spi Serial E 2 Prom With Block Lock ? Protection
• Manufacturer: IC MICROSYSTEMS

X25170
Figure 3. Write Enable Latch Sequence
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figure 4. Byte Write Operation Sequence
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. This sequence is shown in Figure 6.
While the write is in progress following a status register
or E
read to check the WIP bit. During this time the WIP bit
will be HIGH.
2
SCK
PROM write sequence, the status register may be
SO
CS
SI
High Impedance
0
1
Instruction
2
SCK
SO
CS
SI
3
4
High Impedance
5
6
0
7
1
15 14 13
8
2
9
3
16 Bit Address
10
4
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
Hold Operation
The HOLD input should be HIGH (at V
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW, and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to
V
5
CC
20 21 22 23 24 25 26 27 28 29 30 31
3
6
or tied to V
2
7
1
0
CC
7
Characteristics subject to change without notice.
through a resistor.
6
5
Data Byte
4
3
2
IH
1
) under normal
0
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